 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 9296c-avr-07/14 features high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture 125 powerful instructions ? mo st single-clock-cycle execution 32 8 general purpose working registers fully static operation high-endurance, nonvolatile memory segments 16kb of in-system, self prog rammable flash program memory endurance: 10 ,000 write/erase cycles 256 bytes of in-system programmable eeprom endurance: 100,000 write/erase cycles 1kb of internal sram data retention: 20 years at 85c/100 years at 25c programming lock for self programmi ng flash and eeprom data security peripheral features dedicated hardware and qtouch ? library support for capacitive touch sensing one 8-bit and one 16-bit timer/counter with two pwm channels, each 12-channel, 10-bit adc programmable ultra-low-power watchdog timer on-chip analog comparator two full duplex usarts with start frame detection universal serial interface slave i 2 c serial interface special microcontroller features debugwire on-chip debug system in-system programmable via spi port internal and external interrupt sources pin change interrupt on 18 pins low-power idle, adc noise reduction, standby and power-down modes enhanced power-on reset circuit programmable brown-out detection circuit with supply voltage sampling calibrated 8mhz oscillator with temperature calibration option calibrated 32khz ultra-low-power oscillator on-chip temperature sensor attiny1634 8-bit avr microcontroller with 16kb in-system programmable flash preliminary datasheet
attiny1634 [preliminary datasheet] 9296c?avr?07/14 2 i/o and packages 18 programmable i/o lines 20-pad qfn/mlf and 20-pin tssop operating voltage: 2.7v to 5.5v speed grade: 0 to 8mhz at 2.7v to 5.5v 0 to 12mhz at 4.5v to 5.5v temperature range: ?40c to +125c low power consumption active mode: 1.2ma at 3v and 4mhz idle mode: 0.23ma at 3v and 4mhz power-down mode (wdt-enabled): 2a at 3v power-down mode (wdt-disabled): 150na at 3v 3 attiny1634 [preliminary datasheet] 9296c?avr?07/14 1. pin configurations figure 1-1. pinout of atmel attiny1634 (pcint8/txd0/adc5) pb0 (pcint7/rxd0/adc4) pa7 (pcint6/oc1b/adc3) pa6 (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 (pcint1/ain0) pa1 (pcint0/aref) pa0 (pcint6/oc1b/adc3) pa6 note bottom pad should be soldered to ground pa7 (pcint7/rxd0/adc4) (pcint1/ain0) pa1 (pcint0/aref) pa0 gnd vcc pb0 (pcint8/txd0/adc5) pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) gnd 1 2 3 4 5 6 7 8 9 10 20 115 2 3 4 5 14 13 12 11 19 18 17 16 678910 20 19 18 17 16 15 14 13 12 11 tssop qfn/mlf pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) pc5 (xtal1/clki/pcint17) vcc (xtal1/clki/pcint17) pc5 attiny1634 [preliminary datasheet] 9296c?avr?07/14 4 1.1 pin descriptions 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 xtal1 input to the inverting amplifier of the oscillator and the intern al clock circuit. this is an alternative pin configuration of pc5. 1.1.4 xtal2 output from the inverting amplifier of the o scillator. alternative pi n configuration of pc4. 1.1.5 reset reset input. a low level on this pin for longer than the mini mum pulse length generates a reset, even if the clock is not running, provided the reset pin has not been disabled. the minimum pulse length is given in table 25-5 on page 218 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1.1.6 port a (pa7:pa0) this is an 8-bit, bidirectional i/o port with internal pull-up re sistors (selected for each bit). output buffers have the follo wing drive characteristics: pa7, pa4:pa0: symmetrical, with standard sink and source capability pa6, pa5: asymmetrical, with high sink and standard source capability as inputs, port pins that are externally pulled low draw current, provided that pull-u p resistors are activated. port pins are tri- stated when a reset condition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device (see section 11.3.1 ?alternate functions of port a? on page 61 ). 1.1.7 port b (pb3:pb0) this is a 4-bit, bidirectional i/o port with internal pull-up re sistors (selected for each bit).o utput buffers have the followi ng drive characteristics: pb3: asymmetrical, with high sink and standard source capability pb2:pb0: symmetrical, with standard sink and source capability as inputs, port pins that are externally pulled low draw current, provided that pull-u p resistors are activated. port pins are tri- stated when a reset condition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device (see section 11.3.2 ?alternate functions of port b? on page 64 ). 1.1.8 port c (pc5:pc0) this is a 6-bit, bidirectional i/o port with internal pull-up resistors (selected for each bit) . output buffers have the follow ing drive characteristics: pc5:pc1: symmetrical, with standar d sink and source capability pc3: weak sink/source pc0: asymmetrical, with high sink and standard source capability as inputs, port pins that are externally pulled low draw current, provided that pull-u p resistors are activated. port pins are tri- stated when a reset condition becomes active, even if the clock is not running. this port has alternate pin functions to serve special features of the device (see section 11.3.3 ?alternate functions of port c? on page 66 ). 5 attiny1634 [preliminary datasheet] 9296c?avr?07/14 2. overview the atmel ? attiny1634 is a low-power cmos 8-bit microcontroller based on the avr ? enhanced risc architecture. by executing powerful instructions in a single clock cycl e, the atmel attiny1634 achieves throughputs appr oaching 1mips per mhz allowing the system designer to optimize power consumption vers us processing speed. figure 2-1. block diagram power supervision: por/bod reset avr ? cpu core on chip debugger isp interface debug interface 8-bit timer/counter 16-bit timer/counter temperature sensor analog comparator to u c h sensing two wire interface voltage reference calibrated ulp oscillator calibrated oscillator watchdog timer program memory (flash) data memory (sram) timing and control eeprom reset gnd v cc usart0 usart1 usi multiplexer adc port a port c port b 8-bit data bus pa[7:0] pb[3:0] pc[5:0] attiny1634 [preliminary datasheet] 9296c?avr?07/14 6 the avr ? core combines a rich instruction set with 32 general purpose working registers. al l 32 registers are directly connected to the arithmetic logic unit (a lu), allowing two independent registers to be accessed in a single instruction and executed in one clock cycle. the resulti ng architecture is compact and code effici ent while achieving throughputs up to ten times faster than conventi onal cisc microcontrollers. the atmel ? attiny1634 provides the following features: 16kb of in-system programmable flash 1kb of sram data memory 256 bytes of eeprom data memory 18 general purpose i/o lines 32 general purpose working registers an 8-bit timer/counter with two pwm channels a16-bit timer/counter with two pwm channels internal and external interrupts a 10-bit adc with 5 internal and 12 external channels an ultra-low-power, programmable watchdog timer with internal oscillator two programmable usarts with start frame detection a slave two-wire interface (twi) a universal serial interface (u si) with start condition detector a calibrated 8mhz oscillator a calibrated 32khz, ultra-low-power oscillator four software-selectable power saving modes the device includes the following modes for saving power: idle mode: stops the cpu while allowi ng the timer/counter, adc, analog comp arator, spi, twi, and interrupt system to continue functioning. adc noise reduction mode: minimizes switching noise during adc conversions by stopping the cpu and all i/o modules except the adc power-down mode: registers keep their contents and all ch ip functions are disabled until the next interrupt or hardware reset. standby mode: the oscillator is running while the rest of the device is sleepi ng, allowing very fast start-up combined with low power consumption. the device is manufactured using high density nonvolatile me mory technology from atmel. the flash program memory can be re-programmed in-system through a serial interface, by a conventional nonvolatile memory programmer or by an on-chip boot code running on the avr core. the atmel attiny1634 avr is supported by a full suite of program and system development tools including c compilers, macro assemblers, program debugger/s imulators, and evaluation kits. 7 attiny1634 [preliminary datasheet] 9296c?avr?07/14 3. automotive quality grade the atmel ? attiny1634 has been developed and manufactured acco rding to the most stringent requirements of the international iso-ts-16949 grade 1 standard. this datasheet contains limit values extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the atmel attiny1634 have been verified during regular product qualification in compliance with aec-q100. as indicated in the ordering information paragraph, the product is available in only one temperature grade. 4. general information 4.1 resources a comprehensive set of drivers, applicat ion notes, datasheets, and descriptions on development tools are available for download at http://www.atmel.com/avr. 4.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part-s pecific header file is included before compila tion. be aware that not all c compiler vendors include bit definitions in the header files and interrupt hand ling in c is compiler-dependent. for more details, see the c compiler documentation. for i/o registers located in the extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi ? and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically, this means ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr? and ?cbr?. note that not all avr ? devices include an extended i/o map. 4.3 capacitive touch sensing atmel qtouch ? library provides an easy-to-use solution for touch- sensitive interfaces on atmel avr microcontrollers. qtouch library includes support for qt ouch and qmatrix acquisition methods. touch sensing is easily added to any application by linking the qtouch library and using the application programming interface (api) of the library to define the touch channels and sensors. the applicat ion then calls the api to retrieve channel information and determine the state of the touch sensor. qtouch library is free and can be downlo aded from the atmel website. for more information and implementation details, see the qtouch library user guide?also available from the atmel website. 4.4 data retention reliability qualification results show that th e projected data retention failure rate is much less than 1ppm over 20 years at 85c or 100 years at 25c. table 3-1. temperature grade identification for automotive products temperature temperature identifier comments ?40c; +125c z full automotive temperature range attiny1634 [preliminary datasheet] 9296c?avr?07/14 8 5. cpu core this section discusses the avr ? core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to acce ss memories, perform calculations, control peripherals, and handle interrupts. 5.1 architectural overview figure 5-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture?with separate memories and buses for program and data. instructions in the program memo ry are executed with single-level pipelining. while one instruction is being executed, the next in struction is pre-fetched from the program memory. this co ncept enables instructions to be executed in every clock cycle. the program memo ry is an in-system reprogrammable flash memory. the fast-access register file c ontains 32 x 8-bit general purpose working regi sters with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu operat ion, two operands are output from the register file, the operation is exec uted and the result is stored back in the register file?in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing?enabling efficient address calculations. on e of these address pointers can also be used as an address pointer for lookup tables in flash program memory. these added function registers are the 16 -bit x, y, and z register de scribed later in this section. the alu supports arithmetic and logic operat ions between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional ju mp and call instructions capable of directly addressing the whole address space. most avr instructions have a single 16-bit word format, but 32-bit-wide instruct ions also exist. the actual instruction set varies because some device s only implement part of the instruction set. direct addressing indirect addressing program counter interrupt unit status and control x alu y z instruction register instruction decoder control lines program memory (flash) data memory (sram) general purpose registers 8-bit data bus 9 attiny1634 [preliminary datasheet] 9296c?avr?07/14 during interrupts and subroutine calls, the return address prog ram counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram and as a result the stack size is only limited by the total sram size and the usage of the sram. all user programs mu st initialize the sp in the reset rout ine (before subroutines or interrupts are executed). the stack pointer (sp) is read /write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr ? architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate interrupt vector in th e interrupt vector table. the interrupts have priority in accord ance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file 0x20 - 0x5f. in addition, the atmel ? attiny1634 has extended i/o space from 0x60 - 0x ff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 5.2 alu ? arithmetic logic unit the high-performance avr alu operates in direct connection wi th all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general pu rpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories?arithmetic, logical, and bit functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. for more info rmation, see the external ?avr instruction set? document and section 28. ?instruction set summary? on page 248 . 5.3 status register the status register contains information about the result of the most rec ently executed arithmetic instruction. this information can be used for altering program flow in order to per form conditional operations. note that the status register is updated after all alu operations. in many cases this make s using the dedicated compare instructions unnecessary, resulting in faster and more compact co de. for more information, see the external ?avr instruction set? document and section 28. ?instruction set summary? on page 248 . the status register is neither automatica lly stored when entering an interrupt routine nor restored when returning from an interrupt. this must be handled by software. 5.4 general purpose register file the register file is optimized for the avr-enhanced risc inst ruction set. in order to achi eve the required performance and flexibility, the following in put/output schemes are supported by the register file: one 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input one 16-bit output operand an d one 16-bit result input attiny1634 [preliminary datasheet] 9296c?avr?07/14 10 figure 5-2 below shows the structure of the 32 gener al purpose working registers in the cpu. figure 5-2. general purpose working registers most of the instructions operating on the register file have dire ct access to all registers, and most of them are single-cycle instructions. as shown in figure 5-2 , each register is also assigned a data memory address, mapping them directly to the first 32 locations of the user data space. although not physically implemented as sram locations, this memory organization provides excellent flexibility when accessing registers because the x, y, and z pointer registers can be set to index any register in the file. 5.4.1 the x, y, and z registers the registers r26..r31 have functions going beyond their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three i ndirect address registers x, y, and z are defined as described in figure 5-3 below. figure 5-3. the x, y, and z registers 70 addr. special function r0 0x00 r1 0x01 r2 0x02 r3 0x03 ? ... r12 0x0c r13 0x0d r14 0x0e r15 0x0f r16 0x10 r17 0x11 ? ... r26 0x1a x register low byte r27 0x1b x register high byte r28 0x1c y register low byte r29 0x1d y register high byte r30 0x1e z register low byte r31 0x1f z register high byte 15 0 x register 7 xh 07 xl 0 r27 r26 15 0 y register 7 yh 07 yl 0 r29 r28 15 0 z register 7 zh 07 zl 0 r31 r30 11 attiny1634 [preliminary datasheet] 9296c?avr?07/14 in the different addressing modes these address registers ha ve fixed displacement, automa tic increment, and automatic decrement functions (see the instru ction set reference for details). 5.5 stack pointer the stack is mainly used for storing te mporary data, local variables, and return addresses after interrupts and subroutine calls. the stack pointer register s (sph and spl) always point to the top of the stack. note that the stack grows from higher memory locations to lower memo ry locations. this means that the push in structions decreases and the pop instruction increases the stack pointer value. the stack pointer points to the data memory area where subroutine and interrupt sta cks are located. this stack space must be defined by the program before any subroutine calls are executed or interrupts are enabled. the pointer is decremented by one when data is put on the st ack with the push instruction, and incremented by one when data is fetched with the pop in struction. it is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from a subroutine (the ret instruction) or a return from an interrupt service routine (the reti instruction). the avr ? stack pointer is typically implemented as two 8-bit register s in the i/o register file. the width of the stack pointer and the number of bits implemented is device-dependent. in some avr devices all data memory can be addressed using spl only. in this case the sph register is not implemented. the stack pointer must be set to point above the i/o register areas, the minimum value being the lowest sram address. for more information, see table 6-2 on page 17 . 5.6 instruction execution timing this section describes the general access timing concepts fo r instruction execution. the avr cpu is driven by the cpu clock clk cpu which is generated directly from the selected chip clock source. no internal clock division is used. figure 5-4 shows the parallel instruction fetches and instruction exec utions enabled by the harvar d architecture and the fast access register file concept. this is the basic pipelining co ncept for obtaining up to 1mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power unit. figure 5-4. the parallel instructio n fetches and instruction executions clk cpu 1st instruction fetch 1st instruction execute 2nd instruction fetch t1 t2 t3 t4 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch attiny1634 [preliminary datasheet] 9296c?avr?07/14 12 figure 5-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed with the result stored back to the destination register. figure 5-5. single cycle alu operation 5.7 reset and interrupt handling the avr ? provides several different interrupt sources. these in terrupts and the separate reset vector each have a separate program vector in the program memory sp ace. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in t he status register in order to enable the interrupt. the lowest addresses in the program memo ry space are defined as the reset and in terrupt vectors by default. the complete list of vectors is shown in section 10. ?interrupts? on page 47 . the list also determines the prio rity levels of the different interrupts. the lower the address, the higher the priority level. reset has the highest priority, followed by int0?the external interrupt request 0. when an interrupt occurs, the global interrupt enable i bit is cl eared and all interrupts are disa bled. the user software can write logic one to the i bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routi ne. the i bit is automatically set w hen a return from interrupt instruction (reti) is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interr upt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bi t position(s) to be cleared. if an interrupt condition occurs while the corres ponding interrupt enable bit is cleared, the interr upt flag is set and remembered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interr upt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) is (are) set and remembered until the global interrupt enable bit is set, at which point it is executed based on its priority. the second type of interrupts triggers as long as the interr upt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt is not triggered. when the avr exits from an interrupt, it always returns to th e main program and executes one more instruction before any pending interrupt is served. note that the status regi ster is not automatically stored when entering an in terrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the inte rrupts are immediately disabled. no interrupt is executed after the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. clk cpu t1 register operands fetch result write back alu operation execute total execution time t2 t3 t4 13 attiny1634 [preliminary datasheet] 9296c?avr?07/14 note: see section 4.2 ?code examples? on page 7 . when using the sei instruction to enable in terrupts, the instruction following sei is executed before any pending interrupts as shown in the following example. note: see section 4.2 ?code examples? on page 7 . 5.7.1 interrupt response time the minimum interrupt execution response for all the enabled avr ? interrupts is four clock cycles . after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four-clock-cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the inte rrupt routine and this jump takes three clock cycles. if an interrupt occurs du ring execution of a multi-cycle in struction, this inst ruction is completed before the interrup t is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the sleep mode selected. a return from an interrupt hand ling routine takes four clock cycl es. during these four clock cycl es, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two and the i bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 15 attiny1634 [preliminary datasheet] 9296c?avr?07/14 5.8.3 sreg ? status register bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled regardless of the individual interrupt enabl e settings. the i bit is cleared by hardware after an interrupt has occurred and is set by the reti instruction to enable subsequent interrupts. t he i bit can also be set and cleared by the application with the sei and cli instructions as described in the instruction set reference. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) us e the t bit as the source or destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register f ile by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is useful in bcd arithmetic. for more information, see the ?instruction set description? section. bit 4 ? s: sign bit, s = n v the s bit is always an exclusive or between the negative fl ag n and the two?s complement overflow flag v. for more information, see the ?instruction set description? section. bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. for more information, see the ?instruction set description? section. bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logi c operation. for more information, see the ?instruction set description? section. bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. for more information, see the ?instruction set description? section. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logi c operation. for more information, see the ?instruction set description? section. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 16 6. memories the avr ? architecture makes a distinction between program memo ry and data memory, locating each memory type in a separate address space. executable code is located in nonvolat ile program memory (flash), whereas data can be placed in either volatile (sram) or non volatile memory (eeprom) (see figure 6-1 ). figure 6-1. memory overview all memory spaces are linear and regular. 6.1 program memory (flash) the atmel ? attiny1634 contains 16kb of on-ch ip, in-system reprogrammable flash me mory for program storage. flash memories are nonvolatile, i.e., they retain stored information even when not powered. because all avr instructions are 16 or 32 bits wide, the flas h is organized as 8192 x 16 bits. the program counter (pc) is 13 bits wide and thus capable of addressing all 81 92 locations of program memory as illustrated in table 6-1 . constant tables can be allocated within the entire address space of program memory. see the lpm (load program memory) and spm (store program memory) instructions in section 28. ?instruction set summary? on page 248 . flash program memory can also be programmed from an external device as described in section 24. ?external programming? on page 202 . timing diagrams for instruction fetc h and execution are presented in section 5.6 ?instruction execution timing? on page 11 . the flash memory has a minimum endur ance of 10,000 wr ite/erase cycles. program memory data memory sram data memory eeprom i/o register file extended i/o register file general purpose register file flash table 6-1. size of program memory (flash) device flash size address range atmel attiny1634 16kb 8192 words 0x0000 ? 0x1fff 17 attiny1634 [preliminary datasheet] 9296c?avr?07/14 6.2 data memory (sram) and register files table 6-2 shows how the data memory and register files of the atmel ? attiny1634 are organized. these memory areas are volatile, i.e., they do not retain information when power is off or interrupted. the 1280 memory locations include the general purpose register file, i/o register file, extende d i/o register file, and the internal data memory. for compatibility with future devices, reserved bits should be written to ?0? if accessed. reserved i/o memory addresses should never be written. 6.2.1 general purpose register file the first 32 locations are reserved for the general purpose register file. these registers are described in detail in section 5.4 ?general purpose register file? on page 9 . 6.2.2 i/o register file following the general purpose register file, the next 64 location s are reserved for i/o registers. registers in this area are used mainly for communicating with i/o and peripheral units of the device. data can be transferred between i/o space and the general purpose register file using instructions such as in, out, ld, st, and derivatives. all i/o registers in this area can be acce ssed with the instructions in and out. these i/o specific instructions address the first location in the i/o register area as 0x00 and the last as 0x3f. the low 32 registers (address range 0x00...0x1f) are accessible by some bit-specific instructions. in these registers, bits are easily set and cleared using sbi and cbi, while bit-conditiona l branches are readily constr ucted using sbic, sbis, sbrc, and sbrs instructions. registers in this area may also be accessed with ld/ldd/lds and st/std/sts instructions. these instructions treat the entire volatile memory as one data space and as a result address i/o registers starting at 0x20. for more information, see section 28. ?instruction set summary? on page 248 . the atmel attiny1634 also contains three general purpose i/o registers that can be used for storing any information (see gpior0, gpior1, and gpior2 in section 27. ?register summary? on page 245 ). these general purpose i/o registers are particularly useful for storing global variables and status flags because they are accessible to bit-specific instructions such as sbi, cbi, sbic, sbis, sbrc, and sbrs. 6.2.3 extended i/o register file following the standard i/o register file, the next 160 locations are reserved for extended i/o registers. the attiny1634 is a complex microcontroller with more peripheral units than can be addressed with the in and out instructions. registers in the extended i/o area must be accessed using ld/l dd/lds and st/std/sts instructions (see section 28. ?instruction set summary? on page 248 ). see section 27. ?register summary? on page 245 for a list of i/o registers. table 6-2. layout of data memory and register area device memory area size long address (1) short address (2) atmel attiny1634 general purpose register file 32b 0x0000 ? 0x001f n/a i/o register file 64b 0x0020 ? 0x005f 0x00 ? 0x3f extended i/o register file 160b 0x0060 ? 0x00ff n/a data sram 1024b 0x0100 ? 0x04ff n/a note: 1. also known as data address. this mode of addressing covers the entire data memory and register area. the address is contained in a 16-bit area of two-word instructions. 2. also known as direct i/o address. this mode of addressi ng covers part of the register area only. it is used by instructions where the address is embedded in the instruction word. attiny1634 [preliminary datasheet] 9296c?avr?07/14 18 6.2.4 data memory (sram) following the general purpose register file and the i/o register files, the remain ing 1024 locations are reserved for the internal data sram. there are five addressing modes available: direct ? this mode of addressing reaches the entire data space. indirect indirect with displacement ? this mode of addressing re aches 63 address locations from the base address given by the y or z register. indirect with pre-decrement ? in this mode the address register is automatically decremented before access. address pointer registers (x, y, and z) are lo cated in the general purpose register file, in registers r26 to r31 (see section 5.4 ?general purpose register file? on page 9 ). indirect with post-increment ? in this mode the address register is automatica lly incremented afte r access. address pointer registers (x, y, and z) are lo cated in the general purpose register file, in registers r26 to r31 (see section 5.4 ?general purpose register file? on page 9 ). all addressing modes can be used on the entire volatile memory, in cluding the general purpose regi ster file, the i/o register files, and the data memory. internal sram is accessed in two clk cpu cycles as illustrated below in figure 6-2 . figure 6-2. on-chip data sram access cycles 6.3 data memory (eeprom) the atmel ? attiny1634 contains 256 bytes of nonvolat ile data memory. this eeprom is organized as a separate data space in which single bytes can be read and written. all access registers are located in the i/o space. the eeprom memory layout is summarized in table 6-3 . the internal 8mhz oscillator is used to time eeprom operations. the frequency of the oscillator mu st be within the requirements as described in section 7.5.3 ?osccal0 ? oscillato r calibration register? on page 32 . clk cpu t1 data data rd wr address valid compute address next instruction write read memory access instruction a ddress t2 t3 table 6-3. size of nonvolatile data memory (eeprom) device eeprom size address range atmel attiny1634 256b 0x00 ? 0xff 19 attiny1634 [preliminary datasheet] 9296c?avr?07/14 when powered by heavily filtered supplies, the supply voltage, v cc , is likely to rise or fall slowly on power-up and power- down. slow rise and fall times may put the device in a state w here it is running at supply volt ages lower than specified. to avoid problems in such situations, see section 6.3.5 ?preventing eepr om corruption? on page 20 . the eeprom has a minimum endurance of 100,000 write/erase cycles. 6.3.1 programming methods there are two methods for eeprom programming: atomic byte programming ? this is the simple mode of pr ogramming where target locations are erased and written in a single operation. in this operating mode the target is guaranteed to always be erased before writing but programming times are longer. split byte programming ? it is possible to split the erase a nd write cycle into two different operations. this is useful when short access times are required, for example, when supply voltage is falling. in order to take advantage of this method, target locations must be erased before writing to them. this can be done at times when the system allows time-critical operations, typically at start-up and initialization. the programming method is selected using the eeprom programming mode bits (eepm1 and eepm0) in the eeprom control register (eecr) (see table 6-4 on page 23 ). the write and erase times are given in the same table. because eeprom programming takes some time, the application must wait for one operation to complete before starting the next. this can be done by either polling the eeprom pr ogram enable bit (eepe) in the eeprom control register (eecr), or via the eeprom ready inte rrupt. the eeprom interrupt is controlled by the eepro m ready interrupt enable (eerie) bit in eecr. 6.3.2 read to read an eeprom memory locati on, follow the procedure below: 1. poll the eeprom program enable bit (eepe) in the eeprom control register (eecr) to make sure no other eeprom operations are in proces s. if set, wait to clear. 2. write the target address to the eeprom address registers (eearh/eearl). 3. start the read operation by setting the eeprom read enable bit (eere) in the eeprom control register (eecr). during the read operation, the cpu is stopped for four clock cycles before executing the next instruction. 4. read data from the eeprom data register (eedr). 6.3.3 erase in order to prevent unintentional eeprom writes, a specific procedure must be followed to erase memory locations. to erase an eeprom memory location , follow the procedure below: 1. poll the eeprom program enable bit (eepe) in the eeprom control register (eecr) to make sure no other eeprom operations are in proces s. if set, wait to clear. 2. set mode of programming to erase by writing the eepr om programming mode bits (eepm0 and eepm1) in the eeprom control register (eecr). 3. write the target address to the eeprom address registers (eearh/eearl). 4. enable erase by setting the eeprom master program enable (eempe) in the eeprom control register (eecr). within four clock cycles, start the erase operation by setting the eeprom program enable bit (eepe) in the eeprom control register (eecr). duri ng the erase operat ion, the cpu is stopped fo r two clock cycles before executing the next instruction. the eepe bit remains set until the erase opera tion has completed. while th e device is busy programming, it is not possible to perform any othe r eeprom operations. attiny1634 [preliminary datasheet] 9296c?avr?07/14 20 6.3.4 write in order to prevent unintentional eeprom writes, a specific procedure must be followed to write to memory locations. before writing data to eeprom, the target location must be eras ed. this can be done either in the same operation or as part of a split operation. writing to an unerased eeprom location results in corrupted data. to write an eeprom memory locati on, follow the procedure below: 1. poll the eeprom program enable bit (eepe) in the eeprom control register (eecr) to make sure no other eeprom operations are in proces s. if set, wait to clear. 2. set the mode of programming by writing the eeprom programming mode bits (eepm0 and eepm1) in the eeprom control register (eecr). alternatively, data can be written in one operation or the write procedure can be split up in erase only and write only. 3. write the target address to the eeprom address registers (eearh/eearl). 4. write the target data to the eeprom data register (eedr). 5. enable write by setting the eeprom master program enable (eempe) in the eeprom control register (eecr). within four clock cycles, start the write operation by setting the eeprom program enable bit (eepe) in the eeprom control register (eecr). during the write operation, the cpu is stopped for two clock cycles before exe- cuting the next instruction. the eepe bit remains set until the write o peration has completed. while the device is busy with programming, it is not possible to do any other eeprom operations. 6.3.5 preventing eeprom corruption during periods of low v cc , the eeprom data may become corrupted because the supply voltage is too low for the cpu and the eeprom to operate properl y. these issues are the same as for boar d-level systems using eeprom; thus the same design solutions should be applied. at low supply voltages data in eeprom may become corrupted in two ways: the supply voltage is too low to maintain proper operation of an otherwise legitimate eeprom program sequence. the supply voltage is too low for the cpu and instructions may be executed incorrectly. eeprom data corruption is avoided by keeping the device in rese t during periods of insufficient power supply voltage. this is easily done by enabling the internal brown-out detector (bod). if bod detection levels are no t sufficient for the design, an external reset circuit for low v cc can be used. provided that supply voltage is sufficient, an eeprom write operation is completed even when a reset occurs. 21 attiny1634 [preliminary datasheet] 9296c?avr?07/14 6.3.6 program examples the following code examples show one assembly and one c func tion for erase, write, or atom ic write of the eeprom. the examples assume that interrupts are controlled (such as by di sabling interrupts globally) so that no interrupts occur during execution of these functions. note: see section 4.2 ?code examples? on page 7 . note: see section 4.2 ?code examples? on page 7 . assembly code example eeprom_write: ; wait for completion of previous write sbic eecr, eepe rjmp eeprom_write ; set programming mode ldi r16, (0< attiny1634 [preliminary datasheet] 9296c?avr?07/14 24 bit 1 ? eepe: eeprom program enable this is the programmi ng enable signal of the eeprom. the eempe bit must be set before eepe is written, otherwise eeprom is not programmed. when eepe is written, the eeprom is programmed accordin g to the eepmn bit settings. when eepe has been set, the cpu is stopped for two cycles before the next instruction is executed. after the write access time has elapsed, the eepe bit is cleared by the hardware. note that an eeprom write operatio n blocks all software pr ogramming of flash, fuse bits, and lock bits. bit 0 ? eere: eeprom read enable this is the read strobe of the eeprom. when the target address has been se t up in the eear, the eere bit must be written to ?1? to trigger the eeprom read operation. eeprom read access takes one instruction an d the requested data is available immediately. w hen the eeprom is read, the cpu is stopped for four cycles befor e the next instruction is executed. the user should poll the eepe bit before starting the read operatio n. if a write operation is in progress, it not possible to r ead the eeprom or to change th e address register (eear). 6.4.4 gpior2 ? general purpose i/o register 2 this register may be used freely for storing any kind of data. 6.4.5 gpior1 ? general purpose i/o register 1 this register may be used freely for storing any kind of data. 6.4.6 gpior0 ? general purpose i/o register 0 this register may be used freely for storing any kind of data. bit 76543210 0x16 (0x36) msb lsb gpior2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x15 (0x35) msb lsb gpior1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x14 (0x34) msb lsb gpior0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 25 attiny1634 [preliminary datasheet] 9296c?avr?07/14 7. clock system figure 7-1 presents the principal clock system s and their distri bution in atmel ? attiny1634. not all of the clocks need to be active at a given time. in order to reduc e power consumption, the clocks to modules not being used can be stopped by using different sleep modes and power reduction register bits as described in section 8. ?power management and sleep modes? on page 34 . the clock systems can be seen in detail below. figure 7-1. clock distribution 7.1 clock subsystems the clock subsystems are describ ed in the following sections. 7.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of t he system concerned with operation of the avr ? core. examples of such modules are the general purpose register file, the status register and the data memory holding the stack pointer. stopping the cpu clock inhibits the core from performing ge neral operations and calculations. 7.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, such as the timer/counter module. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is stopped. avr clock control unit crystal oscillator calibrated internal oscillator external clock watchdog clock flash and eeprom general i/o modules system clock prescaler adc cpu core ram reset logic watchdog timer 32khz ulp oscillator clk i/o clk adc clk cpu clk flash clock multiplexer attiny1634 [preliminary datasheet] 9296c?avr?07/14 26 7.1.3 flash clock ? clk flash the flash clock controls operation of the flash interfac e. the flash clock is usually active with the cpu clock simultaneously. 7.1.4 adc clock ? clk adc the adc has a dedica ted clock domain. this a llows the cpu and i/o clocks to be stopped in order to reduce noise generated by digital circuitry, resulting in more accurate adc conversion results. 7.2 clock sources the device can use any of the follo wing sources for the system clock: see section 7.2.1 ?external clock? on page 26 see section 7.2.2 ?calibrated internal 8mhz oscillator? on page 27 see section 7.2.3 ?internal 32khz ultra- low-power (ulp) oscillator? on page 27 see section 7.2.4 ?crystal oscillato r/ceramic resonator? on page 27 the clock source is sele cted using either cksel bits in the clksr regi ster or cksel fuses. the difference between cksel fuses and bits is that c ksel fuses are automatically loaded to cksel bits at device power-on or at re set. the initial value of cksel bits is therefore determi ned by cksel fuses. cksel fuse bits can be read by firmware (see section 23.4 ?reading lock, fuse, and signature data from software? on page 200 ), but firmware cannot write to fuse bi ts. the cksel bits must thus be used if the system clock source needs to be changed at run time. the clock system has been designed to guarantee glitch-free perfo rmance when switching between clock sources (see section 7.5.1 ?clksr ? clock setting register? on page 29 ). when the device wakes up from power-down, the selected cloc k source is used to time the start-up, ensuring stable oscillator operation before instruction ex ecution starts. when the cpu st arts from reset, the internal 32khz oscillator is used for generating an additional delay, allowing supply voltage to reach a stable level before normal device operation is started. system clock alternatives are discussed in the following sections. 7.2.1 external clock to drive the device from an external clock source, clki should be connected as shown in figure 7-2 . sudden changes in the external clock frequency should a lways be avoided to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the nex t can lead to unpr edictable behavior. ensure that the mcu is kept in reset during changes of clock frequency of this magnitude. stable operation for large step changes in system clock freq uency is guaranteed when using the system clock prescaler (see section 7.3 ?system clock prescaler? on page 28 ). figure 7-2. external clock drive configuration start-up time for this clock source is determined by the sut bit as shown in table 7-2 on page 29 . clki gnd external clock signal 27 attiny1634 [preliminary datasheet] 9296c?avr?07/14 7.2.2 calibrated intern al 8mhz oscillator the internal 8mhz oscillator operates with no external co mponents and, by default, provides a clock source with an approximate frequency of 8mhz. though vo ltage- and temperature-dependent, this cl ock can be very accurately calibrated by the user. for more information, see table 25-2 on page 217 , section 26-39 ?calibrated oscillator frequency (nominal = 1mhz) versus v cc ? on page 243 and section 26-40 ?calibrated oscillator frequen cy (nominal = 1mhz) versus temperature? on page 244 . during reset, the hardware loads the preprogrammed calibra tion value into the osccal0 register and automatically calibrates the oscillator at the same ti me. for more information on automatic l oading of preprogrammed calibration values, see section 23.3.2 ?calibration bytes? on page 199 . it is possible to reach higher accuracies than factory defa ults, especially when the application allows temperature and voltage ranges to be narrowed. the firmware can reprogram the ca libration data in osccal0 either at start-up or during run time. the continuous run-time calibration method allows fi rmware to monitor voltage and temperature and compensate for any detected variations (see section 7.5.3 ?osccal0 ? oscillator calibration register? on page 32 , section 20.12 ?temperature measurement? on page 182 and table 20-3 on page 183 ). the accuracy of this calibration is referred to as ?user calibration? in table 25-2 on page 217 . the osctcal0a and osctcal0b oscillator temperature calib ration registers can be used for one-time temperature calibration of oscillator frequency. for more information, see section 7.5.4 ?osctcal0a ? oscillator temperature calibration register a? on page 32 and section 7.5.5 ?osctcal0b ? oscillator te mperature calibration register b? on page 33 . during reset, hardware loads the preprogrammed cali bration values into the osctcal0a and osctcal0b registers. start-up time for this clock source is determined by the sut bit as shown in table 7-2 on page 29 . 7.2.3 internal 32khz ultra-low-power (ulp) oscillator the internal 32khz oscillator is a low-power oscillator that oper ates with no external components. it provides a clock source with an approximate frequency of 32khz. the frequency depends on supply voltage, te mperature, and batch variations. for more details on accuracy, see table 25-3 on page 217 . during reset, the hardware loads the preprogrammed calibra tion value into the osccal1 register and automatically calibrates the oscillator at the same time. the accuracy of this calibration is referred to as ?factory calibration? in table 25-3 on page 217 . for more information on automatic loading of preprogrammed calibration value, see section 23.3.2 ?calibration bytes? on page 199 . when this oscillator is used as the chip clock, it is still used for the watchdog timer and for the reset time-out. start-up time for this clock source is determined by the sut bit as shown in table 7-2 on page 29 . 7.2.4 crystal oscillator/ceramic resonator xtal1 and xtal2 are input and output, respectively, of an inve rting amplifier which can be configured for use as an on-chip oscillator as shown in figure 7-3 . a quartz crystal or a ceramic resonator may be used. figure 7-3. crystal oscillator connections c2 xtal2 xtal1 gnd c1 attiny1634 [preliminary datasheet] 9296c?avr?07/14 28 capacitors c1 and c2 should always be equal, both for crys tals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electr omagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are indicated in table 7-1 . the capacitor values given by the manufacturer should be used for ceramic resonators. the oscillator can operate in di fferent modes, each optimized for a specific frequency range (see table 7-4 on page 31 ). start-up time for this clock source is determined by the sut bit as shown in table 7-2 on page 29 . 7.2.5 default clock settings the device is shipped with the following fuse settings: calibrated internal 8mhz oscillator (see cksel bits on 30 ) longest possible start-up time (see sut bit on 29 ) system clock prescaler set to 8 (see ckdiv8 fuse bit on 198 ) the default setting result s in a 1mhz system clock and ensur es all users can make their desir ed clock source setting using an in-system or high-voltage programmer. 7.3 system clock prescaler the atmel ? attiny1634 system clock can be divided by selecting the setting shown in section 7.5.2 ?clkpr ? clock prescale register? on page 31 . this feature allows power consumption to be reduced when little processing power is required. the feature can also be used wi th all clock source options and affects the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu and clk flash are divided by a factor shown in table 7-4 on page 31 . 7.3.1 switching prescaler setting when switching between prescaler settings, the system clock pr escaler ensures that no glitch occurs in the clock system and that no intermediate frequency is higher than either the clock frequency correspond ing to the previous setting or the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the fr equency of the undivided clock, which may be faster than the cpu?s clock frequency. this means it is not possible to determ ine the state of the prescaler?even if it were readable and the exact time it takes to switch from one cloc k division to another could not be predicted exactly. from the time the clkps values are writte n, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, two active clock edges are produced. here, t1 is the previous clock period and t2 is the period corresponding to the new prescaler setting. 7.4 clock output buffer the device can output the system clock on the clko pin. to enable the output, the ckout_io bit has to be programmed. the ckout fuse determines the initial value of the ckout_io bi t that is loaded to the clksr register when the device is powered up or has been reset. the clock output can be switched at run time by setting the ckout_io bit in clksr as described in section 7.5.1 ?clksr ? clock setting register? on page 29 . this mode is suitable wh en the chip clock is used to driv e other circuits on the system. note that the clock is not output during reset and that the normal operation of the i/o pin is overridden when the fuse is programmed. any clock source, including the internal oscillators, can be selected when the clo ck is output on clko. if the s ystem clock prescaler is used, the divided system clock is output. table 7-1. crystal oscillator operating modes frequency range recommended c1 and c2 note < 1mhz ? crystals only. not ceramic resonators. > 1mhz 12 ? 22pf 29 attiny1634 [preliminary datasheet] 9296c?avr?07/14 7.5 register description 7.5.1 clksr ? clock setting register bit 7 ? oscrdy: oscillator ready this bit is set when oscillator time-out is complete. when oscrdy is set, the oscillator is stab le and the clock source can be changed safely. bit 6 ? cstr: clock select trigger this bit triggers the clock selection. it can be used to enable th e oscillator in advance and select the clock source before th e oscillator is stable. if cstr is set at the same time as the c ksel bits are written, the contents are direct ly copied to the c ksel register and the system clock is immediately switched. if cksel bits are written without setting cstr, the oscillator selected by the cksel bits is enabled, but the system clock is not yet switched. bit 5 ? ckout_io: clock output this bit enables the clock output buffer. the ckout fuse determi nes the initial value of the ckou t_io bit that is loaded to the clksr register when the device is powered up or has been reset. bit 4 ? sut: start-up time the sut and cksel bits define the start- up time of the device as shown in table 7-2 below. the initial value of the sut bit is determined by the sut fuse. the sut fuse is loaded to the sut bit when the device is powered up or has been reset. bit 76 5 43210 0x32 (0x52) oscrdy cstr ckout_io sut cksel3 cksel2 cksel1 cksel0 clksr read/write r w r r r/w r/w r/w r/w initial value 0 0 0 see bit description table 7-2. device start-up times sut cksel clock from power-down (1)(2) from reset (3) 0 (4) 0000 external 6 ck 22 ck + 16ms 0010 (4) internal 8mhz 6 ck 20 ck + 16ms 0100 internal 32khz 6 ck 22 ck + 16ms 0001 0011 0101 ... 0111 reserved 1xx0 ceramic resonator (5) 258 ck (6) 274 ck + 16ms 1xx1 crystal oscillator 16k ck 16k ck + 16ms note: 1. device start-up time from power-down sleep mode. 2. when bod has been disabled by software, the wake-up time from sleep mode is approximately 60s to ensure the bod is working correctly before mcu continues executing code. 3. device start-up time after reset. 4. the device is shipped with this option selected. 5. this option is not suitable for use with crystals. 6. this option should not be used when operating close to the maximum frequency of the device and only if fre- quency stability at start-up is not important for the application. 7. this option is intended for use with ceramic resonators and will ensure frequency stability at start-up. it can also be used with crystals when not operating close to the maximum frequency of the device and if frequency stability at start-up is not important for the application. attiny1634 [preliminary datasheet] 9296c?avr?07/14 30 bits 3:0 ? cksel[3:0]: clock select bits these bits select the clock source of the system clock and ca n be written at run time. the clock system ensures glitch-free switching of the clock source. cksel fuses determine the initial value of the cksel bits when the device is powered up or reset. the clock alternatives are shown in table 7-3 below. note: 1. for all fuses, ?1? means unprogrammed and ?0? means programmed. 2. this is the default setting. the device is shipped with this fuse combination. to avoid unintentional switching of clock source, when ch anging the cksel bits, a protec ted change sequence must be observed as follows: 1. write the signature for change enable of protected i/o register to register ccp. 2. within four instruction cycles, write the cksel bits with the desired value. 1 0000 ... 0111 1xx1 reserved 1xx0 ceramic resonator 1k ck (7) 1k ck +16ms table 7-3. device clocking options cksel[3:0] (1) frequency device clocking option 0000 any external clock (see 26 ) 0010 8mhz calibrated internal 8mhz oscillator (see 27 ) (2) 0100 32khz internal 32khz ultra-low-pow er (ulp) oscillator (see 27 ) 00x1 0101 ... 0111 ? reserved 100x 0.4...0.9mhz crystal oscillator/ceramic resonator (see 27 ) 101x 0.9...3mhz 110x 3...8mhz 111x > 8mhz table 7-2. device start-up times (continued) sut cksel clock from power-down (1)(2) from reset (3) note: 1. device start-up time from power-down sleep mode. 2. when bod has been disabled by software, the wake-up time from sleep mode is approximately 60s to ensure the bod is working correctly before mcu continues executing code. 3. device start-up time after reset. 4. the device is shipped with this option selected. 5. this option is not suitable for use with crystals. 6. this option should not be used when operating close to the maximum frequency of the device and only if fre- quency stability at start-up is not important for the application. 7. this option is intended for use with ceramic resonators and will ensure frequency stability at start-up. it can also be used with crystals when not operating close to the maximum frequency of the device and if frequency stability at start-up is not important for the application. 31 attiny1634 [preliminary datasheet] 9296c?avr?07/14 7.5.2 clkpr ? clock prescale register bits 7:4 ? res: reserved bits these bits are reserved and always read as ?0?. bits 3:0 ? clkps[3:0]: clock prescaler select bits 3 - 0 these bits define the division factor between the selected cl ock source and the internal system clock. these bits can be written at run time to vary the clock frequency to meet the application requirements. because the divider divides the master clock input to the mcu, the speed of all synchronous peripherals is reduced when a division factor is used. the division factors are found in table 7-4 on page 31 . to avoid unintentional changes of clo ck frequency, when changing the clkps bits, a protected change sequence must be observed as follows: 1. write the signature for change enable of protected i/o register to register ccp. 2. within four instruction cycles, wr ite the desired value to clkps bits. interrupts must be disabled when changing prescaler setti ng to make sure the write pr ocedure is not interrupted. note: 1. this is the initial value when the ckdiv8 fuse has been unprogrammed. 2. this is the initial value when the ckdiv8 fuse has been programmed. the device is shipped with the ckdiv8 fuse programmed. the initial value of clock prescaler bits is determined by the ckdiv8 fuse (see table 23-5 on page 198 ). when ckdiv8 is unprogrammed, the system clock prescaler is set to ?1? and, w hen programmed, to ?8?. any value can be written to the clkps bits regardless of the ckdiv8 fuse bit setting. when ckdiv8 is programmed, the initial value of clkps bits result in a clock division factor of eight at start-up. this is useful when the selected clock source has a higher frequency than allowed under the existing operating conditions (see section 25.3 ?speed? on page 217 ). bit 76543210 0x33 (0x53) ? ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description table 7-4. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0 0 0 0 1 (1) 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 (2) 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 reserved 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 attiny1634 [preliminary datasheet] 9296c?avr?07/14 32 7.5.3 osccal0 ? oscillator calibration register although temperature slope and frequency are in part contro lled by the osctcal0a and osctcal0b registers, it is possible to replace factory calibration by simply writing to th is register only. optimal accuracy is achieved when osccal0, osctal0a, and osctcal0b are calibrated together. bits 7:0 ? cal0[7:0]: osci llator calibration value the oscillator calibration register is used to trim the internal 8mhz oscillator a nd to remove process variations from the oscillator frequency. a preprogra mmed calibration value is automatically written to this register during chip reset, resulting in the factory-calibrated frequency specified in table 25-2 on page 217 . the application software can write this re gister to change the oscillator frequen cy. the oscillator can be calibrated to frequencies specified in table 25-2 on page 217 . calibration outside this range is not guaranteed. the lowest oscillator frequency is reached by programming these bits to ?0?. increasing the register value increases the oscillator frequency. a typical fr equency response curve is shown in section 26-38 ?calibrated oscillator frequency (nominal = 8mhz) versus osccal value? on page 243 . note that this oscillator is used to time eeprom and flash wr ite accesses and that this has a corresponding effect on write times. do not calibr ate to more than 8.8mhz if eeprom or flash is to be written. ot herwise, the eeprom or flash write may fail. to ensure stable operation of the mcu, the calibration value should be chan ged in small steps. a step change in frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. in addition, the difference between two consecutive register values should not exceed 0x20. 7.5.4 osctcal0a ? oscillator temperature calibration register a this register is used for changing the temperature slope a nd frequency of the internal 8mhz oscillator. a preprogrammed calibration value is automatically written to this register du ring chip reset, resulting in the factory-calibrated frequency specified in table 25-2 on page 217 . this register does not need updating if fa ctory defaults in osccal0 ar e overwritten, although opti mal accuracy is achieved when osccal0, osctal0a, and osctcal0b are calibrated together. bit 7 ? sign of oscillator temperature calibration value this is the sign bit of the calibration data. bits 6:0 ? oscillator temperature calibration value these bits contain the numerical value of the calibration data. bit 76543210 (0x63) cal07 cal06 cal05 cal04 cal03 cal02 cal01 cal00 osccal0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device-spec ific calibration value bit 76543210 (0x64) oscillator temperature calibration data osctcal0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device-specific calibration value 33 attiny1634 [preliminary datasheet] 9296c?avr?07/14 7.5.5 osctcal0b ? oscillator temperature calibration register b a preprogrammed calibration value is automatically written to this register during chip reset, resulting in the factory- calibrated frequency specified in table 25-2 on page 217 . this register does not need updating if fa ctory defaults in osccal0 ar e overwritten, although opti mal accuracy is achieved when osccal0, osctal0a, and osctcal0b are calibrated together. bit 7 ? temperature compensation enable when this bit is set, the contents of registers osctcal0a and osctcal0b are used for calibration. when this bit is cleared, the temperature compensation hardware is disabl ed and the osctcal0a and osctcal0b registers have no effect on the frequency of the internal 8mhz oscillator. note that temperature compensation has a strong effect on oscillator frequency and when enabled or disabled, the osccal0 register therefore also must be adjusted to compensate for this effect. bits 6:0 ? temperature compensation step adjust these bits control the step size of the calibration data in osctcal0a. the largest step size is achieved for 0x00 and the smallest step size for 0x7f. 7.5.6 osccal1 ? oscillator calibration register bits 7:2 ? res: reserved bits these bits are reserved and always read as ?0?. bits 1:0 ? cal1[1:0]: osci llator calibration value the oscillator calibration register is used to trim the internal 32khz oscillator and to remove process variations from the oscillator frequency. a preprogra mmed calibration value is automatically written to this register during chip reset, resulting in the factory-calibrated fr equency as specified in table 25-3 on page 217 . the application software can write this re gister to change the oscillator frequen cy. the oscillator can be calibrated to frequencies as specified in table 25-3 on page 217 . calibration outside this range is not guaranteed. the lowest oscillator frequency is reached by programming these bits to ?0?. increasing the register value increases the oscillator frequency. bit 76543210 (0x65) oscillator temperature calibration data osctcal0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device-specific calibration value bit 76543210 (0x66) ? ? ? ? ? ? cal11 cal10 osccal1 read/write r r r r r r r/w r/w initial value device-spec ific calibration value attiny1634 [preliminary datasheet] 9296c?avr?07/14 34 8. power management and sleep modes their industry-leading, high-performance code efficiency makes avr ? microcontrollers an ideal choice for low-power applications. in addition, sleep modes enable the application to shut down unused modules in the mcu and thus save power. the avr provides various sleep modes allowing the user to tailor the power consumption to meet application requirements. 8.1 sleep modes figure 7-1 on page 25 presents the different clock systems and their distribut ion in the atmel ? attiny1634. the figure is helpful for selecting an appropriate sleep mode. table 8-1 shows the different sleep mode s and the sources that may be used for wake-up. notes: 1. start frame detection only. 2. start condition only. 3. address match interrupt only. 4. for int0 level interrupt only. to enter a sleep mode, the se bit in mcucr must be set an d a sleep instruction must be executed. the smn bits in mcucr select what sleep mode is acti vated by the sleep instruction. see table 8-2 on page 37 for a summary. if an enabled interrupt occurs while the mcu is in sleep mo de, the mcu wakes up. the mcu is then stopped for four cycles in addition to the start-up time, executes the interrupt routi ne and resumes execution from th e instruction following sleep. the contents of the register file and sr am are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. note that if a level triggered interrupt is used for wake-up, the changed level must be held for some time to wake up the mcu (and for the mcu to enter the interrupt se rvice routine). for more information, see section 10.2 ?external interrupts? on page 48 . 8.1.1 idle mode this sleep mode ba sically stops clk cpu and clk flash while allowing other clocks to run. in idle mode the cpu is stopped but the following peripherals continue to operate: watchdog and interrupt system analog comparator and adc usart, twi, and timer/counters idle mode allows the mcu to wake up from external triggered interrupts as well as internal ones, such as timer overflow. if wake-up from the analog comparator interrup t is not required, the analog comparator can be powered down by setting the acd bit in acsra (see section 19.2.1 ?acsra ? analog comparator control and status register? on page 170 ). this reduces power consumption in idle mode. if the adc is enabled, a conversion automati cally starts when this mode is entered. table 8-1. active clock domains and wake -up sources in different sleep modes sleep mode oscillators active clock domains wake-up sources main clock source enabled clk cpu clk flash clk io clk adc watchdog interrupt int0 and pin change spm/eeprom ready interrupt adc interrupt usart usi twi slave other i/o idle x x x x x x x x x x x adc noise reduction x x x x (4) x x x (1) x (2) x (3) standby x x x (4) x (1) x (2) x (3) power-down x x (4) x (1) x (2) x (3) 35 attiny1634 [preliminary datasheet] 9296c?avr?07/14 8.1.2 adc noise reduction mode this sleep mode stops clk i/o , clk cpu and clk flash while allowing other clocks to run. in adc noise reduction mode the cpu is stopped but the following peripherals continue to operate: watchdog (if enabled) and external interrupts adc usart start frame detector and twi this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion automatically star ts when this mode is entered. the following events can wake up the mcu: watchdog reset, external reset, and brown-out reset external level interrupt on int0 and pin change interrupt adc conversion complete interrupt and spm/eeprom ready interrupt usi start condition, usart start fr ame detection, and twi address match 8.1.3 power-down mode this sleep mode stops all g enerated clocks, allowin g operation of asynchr onous modules only. in power-down mode the oscillator is stopped while the following peripherals continue to operate: watchdog (if enabled), external interrupts the following events can wake up the mcu: watchdog reset, external reset, and brown-out reset external level interrupt on int0 and pin change interrupt usi start condition, usart start fr ame detection, and twi address match 8.1.4 standby mode standby mode is identical to power-down, with the exception th at the oscillator is kept r unning. from standby mode, the device wakes up in six clock cycles. 8.2 power reduction register the power reduction register (prr) (see section 8.4.2 ?prr ? power reduction register? on page 37 ) provides a method for reducing power consumption by stopping the clock to in dividual peripherals. when the clock for a peripheral is stopped: the current state of the peripheral is frozen. the associated registers cannot be read or written. resources used by the peripheral remain occupied. in most cases, the peripheral should be disabled before stop ping the clock. clearing the prr bit wakes up the peripheral and puts it in the same state as before shutdown. peripheral shutdown can be used in idle mode and active mode to significantly reduce over all power consumption. in all other sleep modes the clock is already stopped. 8.3 minimizing power consumption there are several issues to consider when tr ying to minimize power consumption in an avr ? -controlled system. in general, sleep modes should be used as much as possible and the sleep mode should be selected so that as few as possible of the device?s functions are running. all functi ons not needed should be disabled. in particular, the following modules may need special consideration when trying to achi eve the lowest possible power consumption. 8.3.1 analog to digital converter if enabled, the adc is enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. when the adc is turned off and on again, the next conv ersion is an extended conversion. for more information on adc operation, see section 20. ?analog to digital converter? on page 172 . attiny1634 [preliminary datasheet] 9296c?avr?07/14 36 8.3.2 analog comparator when entering idle mode, the analog comparator should be disabled if it is not being used. when entering adc noise reduction mode, the analog comparator should be disabled. t he analog comparator is automatically disabled in the other sleep modes. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference is enabled, regardless of the sleep mode. for details on how to co nfigure the analog comparator, see section 19. ?analog comparator? on page 169 . 8.3.3 brown-out detector if the brown-out detector is not needed in the application, this module should be turned off. if the brown-out detector is enabled by the bodpd fuses, it is enabled in all sleep mode s and thus always consumes power. in the deeper sleep modes this significantly impacts overall power cons umption. if the brown-out detector is nee ded in the application, this module can also be set to sampled bod mo de to save power. for more information on how to configure the brown-out detector, see section 9.2.4 ?brown-out detection? on page 41 . 8.3.4 internal voltage reference the internal voltage reference is enabled when it is needed by brown-out detection, the analog comparator, or the adc. if these modules are disabled as described in the sections above, the internal voltage reference is disabled and does not consume power. when turned on again, the user must allow th e reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. for more information on the start-up time, see the internal band-gap reference in table 25-5 on page 218 . 8.3.5 watchdog timer if the watchdog timer is not needed in t he application, this module should be turned o ff. if the watchdog timer is enabled, it is enabled in all sleep modes and thus always consumes power . in the deeper sleep modes this impacts overall power consumption. for more information on ho w to configure the watchdog timer, see ?watchdog timer? on page 43 . 8.3.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important thing is to then ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device are disabled. this ens ures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions and will then be enabled. for more information on what pins are enabled, see section 11.2.5 ?digital input enable and sleep modes? on page 57 . if the input buffer is enabled and the input signal is left floating or has an analog signal level close to v cc /2, the input buffer uses excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable register (didr0). for more information, see section 20.13.5 ?didr0 ? digital input disable register 0? on page 186 . 8.3.7 on-chip debug system if the on-chip debug system is enabled by the dwen fuse and the chip enters sleep mode, the main clock source is enabled and thus always consumes power. in the deeper sleep mode s this significantly impacts overall power consumption. 37 attiny1634 [preliminary datasheet] 9296c?avr?07/14 8.4 register description 8.4.1 mcucr ? mcu control register the mcu control register contains control bits for power management. bits 7, 3:2 ? res: reserved bits these bits are reserved and always read as ?0?. bits 6:5 ? sm[1:0]: sleep mode select bits 1 and 0 these bits select between available sleep modes as shown in table 8-2 . note: 1. only recommended with external crys tal or resonator selected as clock source. bit 4 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to keep the mcu from entering sleep mode unless it is the progr ammer?s purpose, atmel recomm ends writing the sleep enable (se) bit to ?1? just before the execution of the sl eep instruction and to clear it immediately after wake-up. 8.4.2 prr ? power reduction register the power reduction register provides a method to reduce power consumption by allowing peripheral clock signals to be disabled. bit 7 ? res: reserved bit this bit is a reserved bit and always reads as ?0?. bit 6 ? prtwi: power reduction two-wire interface writing a logic one to this bit shut s down the two-wire interface module. bit 5 ? prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter 1 module. when timer/counter1 is enabled, operation continues the same way as before the shutdown. bit 4 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter 0 module. when timer/counter0 is enabled, operation continues the same way as before the shutdown. bit 76543210 0x36 (0x56) ?sm1sm0se ? ? isc01 isc00 mcucr read/write r r/w r/w r/w r r r/w r/w initial value00000000 table 8-2. sleep mode select sm1 sm0 sleep mode 0 0 idle 0 1 adc noise reduction 1 0 power-down 1 1 standby (1) bit 76543 2 1 0 0x34 (0x54) ? prtwi prtim1 prtim0 prusi prusart1 prusart0 pradc prr read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 38 bit 3 ? prusi: power reduction usi writing a logic one to this bit shuts down the usi by stoppi ng the clock to the module. when waking up the usi again, the usi should be reinitialized to ensure proper operation. bit 2 ? prusart1: po wer reduction usart1 writing a logic one to this bit shuts do wn the usart1 module. when the usart1 is enabled, operation continues the same way as before the shutdown. bit 1 ? prusart0: po wer reduction usart0 writing a logic one to this bit shuts do wn the usart0 module. when the usart0 is enabled, operation continues the same way as before the shutdown. bit 0 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. the a dc must be disabled before shutdown. the analog comparator cannot be used when the adc is shut down. 39 attiny1634 [preliminary datasheet] 9296c?avr?07/14 9. system control and reset 9.1 resetting the avr during reset, all i/o registers are set to their initial values and the program star ts execution from the reset vector. the instruction placed at the reset vector should be a jmp (two-word, direct jump ) instruction to the reset handling routine, although other one- or two-word jump instructions can be used. if the progra m never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. the circuit diagram in figure 9-1 shows the reset logic. electrical parameters of the reset circuitry are defined in section 25.5 ?system and reset? on page 218 . figure 9-1. reset logic the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is in voked, extending the internal reset period. this allows the power to reach a stable level before normal operation starts. 9.2 reset sources the atmel ? attiny1634 has four sources of reset: power-on reset ? the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). external reset ? the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length when reset function is enabled. watchdog reset ? the mcu is reset when the watchdog timer period expires and the watchdog is enabled. brown-out reset ? the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 9.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in section 25.5 ?system and reset? on page 218 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset as well as to detect a supply voltage failure. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc falls below the detection level. brown out reset circuit spike filter bodlevel2...0 counter reset data bus timeout ck reset flag register (rstflr) power on reset circuit external reset circuit watchdog timer watchdog oscillator rstdisbl clock generator internal reset delay counters pull-up resistor sq r porf wdrf bodrf extrf reset v cc attiny1634 [preliminary datasheet] 9296c?avr?07/14 40 figure 9-2. mcu start-up, reset tied to v cc figure 9-3. mcu start-up, reset extended externally 9.2.2 external reset an external reset is generated by a low level on the reset pin if enabled. reset pulses longer than the minimum pulse width (see section 25.5 ?system and reset? on page 218 ) generate a reset even if the cloc k is not running. shorter pulses are not guaranteed to generate a reset. when the appl ied signal reaches the reset threshold voltage (v rst ) on its positive edge, the delay counter starts the mcu after the time-out period (t tout ) has expired. external reset is ignored during the power- on start-up count. after the reset at power-o n, the internal reset is delayed only i f the reset pin is low when the initial power-on delay count is completed. (see figure 9-2 and figure 9-3 ). figure 9-4. external reset during operation v cc internal reset time-out reset v pot v rst t tout v cc internal reset time-out reset v pot v rst > t tout t tout v cc internal reset time-out reset v rst t tout 41 attiny1634 [preliminary datasheet] 9296c?avr?07/14 9.2.3 watchdog reset when the watchdog times out, it generates a short reset pul se. the delay timer starts c ounting the time-out period t tout on the falling edge of this pulse. see section 9.4 ?watchdog timer? on page 43 for more information about operation of the watchdog timer and table 25-5 on page 218 for more information about the reset time-out. figure 9-5. watchdog reset during operation 9.2.4 brown-out detection the brown-out detection (bod) circuit monitors that the v cc level is kept above a configurable trigger level v bot . when the bod is enabled, a bod reset occurs when v cc falls and remains below the trigger level for the length of the detection time t bod . the reset is kept activated until v cc rises above the trigger level again. figure 9-6. brown-out detection reset v cc internal reset wdt time-out reset time-out reset t tout 1 ck cycle v bot- t bod v bot+ t tout v cc internal reset time-out attiny1634 [preliminary datasheet] 9296c?avr?07/14 42 the bod circuit does not detect a drop in v cc unless the voltage stays below the trigger level for the detection time t bod (see section 25.5 ?system and reset? on page 218 ). the bod circuit has three operating modes: disabled: in this mode v cc is not monitored. it is thus recommended only for applications where the power supply remains stable. enabled: in this mode the v cc level is continuously monitored. if v cc drops below v bot for at least t bod , a brown-out reset is generated. sampled: in this mode the v cc level is sampled on each negative edge of a 1khz clock that has been derived from the 32khz ulp oscillator. the bod is turned off between each sample. compared to the mode where bod is constantly enabled, this operating mode reduces power consumption but fails to detect drops in v cc between two positive edges of the 1khz clock. when a brown-out is detected in this mode, th e bod circuit is set to enabled mode to ensure that the device is kept in reset until v cc has risen above v bot . the bod returns to sampled mode after reset has been released and the fuses have been read in. the bod operating mode is selected usi ng bodact and bodpd fuse bits. the boda ct fuse bits determine how the bod operates in active and idle mode as shown in table 9-1 . the bodpd fuse bits determine the operating mode in all sleep modes except idle mode as shown in table 9-2 . see section 23.2 ?fuse bits? on page 197 . table 9-1. setting bod operating mode in active and idle modes bodact1 bodact0 operating mode 0 0 reserved 0 1 sampled 1 0 enabled 1 1 disabled table 9-2. setting bod operating mode in sleep modes other than idle bodpd1 bodpd0 operating mode 0 0 reserved 0 1 sampled 1 0 enabled 1 1 disabled 43 attiny1634 [preliminary datasheet] 9296c?avr?07/14 9.3 internal voltage reference the atmel ? attiny1634 features an internal band-gap reference. this reference is used for brown-out detection and can be used as an input to the analog comparat or or the adc. the band-gap voltage va ries with supply voltage and temperature. 9.3.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in section 25.5 ?system and reset? on page 218 . to save power, the reference is not a lways turned on. the reference is on during the following situations: 1. when the bod is enabled (see section 9.2.4 ?brown-out detection? on page 41 ) 2. when the internal reference is connected to the analog comparator (by setting the acbg bit in acsra) 3. when the adc is enabled thus, when the bod is not enabled, af ter setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output fr om the analog comparator or adc is used. to reduce power consumption in power- down mode, the user can avoid the three conditions above to en sure that the reference is turned off before entering power- down mode. 9.4 watchdog timer the watchdog timer is clocked from the in ternal 32khz ultra-low-power oscillator (see section 7.2.3 ?internal 32khz ultra- low-power (ulp) oscillator? on page 27 ). by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 9-5 on page 46 . the wdr (watchdog reset) instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a chip rese t occurs. ten different clock-cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the atmel attiny1634 resets and executes from the reset vector. for more information on watchdog reset timing, see table 9-5 on page 46 . the watchdog timer can also be configured to generate an inte rrupt instead of a reset. this can be very helpful when using the watchdog to wake up from power-down. to prevent unintentional disabling of the watchdog or unintentionally changing the time-out period, two different safety levels are selected by the wdton fuse as shown in table 9-3 . for more information, see section 9.4.1 ?timed sequences for changing the configuration of the watchdog timer? on page 44 . figure 9-7. watchdog timer table 9-3. wdt configuration as a func tion of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled timed sequence no limitations programmed 2 enabled always enabled timed sequence osc/512 osc/1k osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k watchdog prescaler mcu reset wdp0 watchdog reset wdp1 wdp2 wdp3 wde 32khz ulp oscillator mux attiny1634 [preliminary datasheet] 9296c?avr?07/14 44 9.4.1 timed sequences for changing the configuration of the watchdog timer the sequence for changing configuration differs slightly betwe en the two safety levels. separate procedures are described for each level. safety level 1 in this mode, the watchdog timer is initially disabled, bu t can be enabled by writing t he wde bit to ?1? without any restriction. a timed sequence is needed when disabling an enabled watchdog timer. to disable an enabled watchdog timer, the following steps must be completed: a. write the signature for change enable of protected i/o registers to register ccp. b. within four instruction cycles, in the same operation, write wde and wdp bits. safety level 2 in this mode, the watchdog timer is always enabled and the wde bit always reads as ?1?. a timed sequence is needed when changing the watchdog time-out period. to ch ange the watchdog time-out, the following steps must be completed: a. write the signature for change enable of protected i/o registers to register ccp. b. within four instruction cycles, write the wd p bit. the value written to wde is irrelevant. 9.4.2 code examples the following code example shows how to turn off the wdt. the example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interr upts occur during execution of these functions. note: see section 4.2 ?code examples? on page 7 . assembly code example wdt_off: wdr ; clear wdrf in rstflr in r16, rstflr andi r16, ~(1< attiny1634 [preliminary datasheet] 9296c?avr?07/14 46 bit 4 ? res: reserved bit this bit is a reserved bit in the atmel ? attiny1634 and always reads as ?0?. bit 3 ? wde: watchdog enable this bit enables and disables the watchdog timer (see section 9.4.1 ?timed sequences for changing the configuration of the watchdog timer? on page 44 ). bits 5, 2:0 ? wdp[3:0]: watchdog timer prescaler 3 - 0 the wdp[3 : 0] bits determine the watchdog timer prescaling when th e watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 9-5 . note: 1. if selected, one of the valid settings below 0b1010 is used. table 9-4. watchdog timer configuration wde wdie watchdog timer state action on time-out 0 0 stopped none 0 1 running interrupt 1 0 running reset 1 1 running interrupt table 9-5. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 wdt oscillator cycles typical time-out @v cc = 5v 0 0 0 0 512 cycles 16ms 0 0 0 1 1k cycles 32ms 0 0 1 0 2k cycles 64ms 0 0 1 1 4k cycles 0.125s 0 1 0 0 8k cycles 0.25s 0 1 0 1 16k cycles 0.5s 0 1 1 0 32k cycles 1.0s 0 1 1 1 64k cycles 2.0s 1 0 0 0 128k cycles 4.0s 1 0 0 1 256k cycles 8.0s 1 0 1 0 reserved (1) 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 47 attiny1634 [preliminary datasheet] 9296c?avr?07/14 10. interrupts this section provides specific information about how the atmel ? attiny1634 handles interrupts. for a general explanation of the avr ? interrupt handling, see section 5.7 ?reset and interrupt handling? on page 12 . 10.1 interrupt vectors the interrupt vectors of the atmel attiny1634 are described in table 10-1 . in case the program never enables an interru pt source, the interrupt vectors are not used. as a result, regular program code can be placed at these locations. table 10-1. reset and interrupt vectors vector no. program address label interrupt source 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset 2 0x0002 int0 external interrupt request 0 3 0x0004 pcint0 pin change interrupt request 0 4 0x0006 pcint1 pin change interrupt request 1 5 0x0008 pcint2 pin change interrupt request 2 6 0x000a wdt watchdog time-out 7 0x000c tim1_capt timer/counter1 input capture 8 0x000e tim1_compa timer/counter1 compare match a 9 0x0010 tim1_compb timer/counter1 compare match b 10 0x0012 tim1_ovf timer/counter1 overflow 11 0x0014 tim0_compa timer/counter0 compare match a 12 0x0016 tim0_compb timer/counter0 compare match b 13 0x0018 tim0_ovf timer/counter0 overflow 14 0x001a ana_comp analog comparator 15 0x001c adc_ready adc conversion complete 16 0x001e usart0_rxs usart0 rx start 17 0x0020 usart0_rxc usart0 rx complete 18 0x0022 usart0_dre usart0 data register empty 19 0x0024 usart0_txc usart0 tx complete 20 0x0026 usart1_rxs usart1 rx start 21 0x0028 usart1_rxc usart1 rx complete 22 0x002a usart1_dre usart1 data register empty 23 0x002c usart1_txc usart1 tx complete 24 0x002e usi_str usi start 25 0x0030 usi_ovf usi overflow 26 0x0032 twi two-wire interface 27 0x0034 ee_rdy eeprom ready 28 0x0036 qtrip qtrip qtouch attiny1634 [preliminary datasheet] 9296c?avr?07/14 48 a typical and general setup for interrupt vector addresses in the atmel ? attiny1634 is shown in the program example below. note: see section 4.2 ?code examples? on page 7 . 10.2 external interrupts external interrupts are triggered by the int0 pin or by any of the pcintn pins. note that, if enabled, the interrupts trigger even if the intn or pcintn pins are configured as outputs. th is feature makes it possible to generate software interrupts. the pin change interrupts trigger as follows: pin change interrupt 0 (pci0): triggers if any enabled pcint[7:0] pin toggles. pin change interrupt 1 (pci1): triggers if any enabled pcint[11:8] pin toggles. pin change interrupt 2 (pci2): triggers if any enabled pcint[17:12] pin toggles. registers pcmsk0, pcmsk1, and pcmsk2 control what pins contribute to the pin change interrupts. pin change interrupts on pcint[17:0] are detected asynchronousl y, meaning these interrupts can also be used for waking the part from sleep modes other than idle mode. assembly code example .org 0x0000 ;set address of next statement jmp reset ; address 0x0000 jmp int0_isr ; address 0x0002 jmp pcint0_isr ; address 0x0004 jmp pcint1_isr ; address 0x0006 jmp pcint2_isr ; address 0x0008 jmp wdt_isr ; address 0x000a jmp tim1_capt_isr ; address 0x000c jmp tim1_compa_isr; address 0x000e jmp tim1_compb_isr; address 0x0010 jmp tim1_ovf_isr ; address 0x0012 jmp tim0_compa_isr; address 0x0014 jmp tim0_compb_isr; address 0x0016 jmp tim0_ovf_isr ; address 0x0018 jmp ana_comp_isr ; address 0x001a jmp adc_isr ; address 0x001c jmp usart0_rxs_isr; address 0x001e jmp usart0_rxc_isr; address 0x0020 jmp usart0_dre_isr; address 0x0022 jmp usart0_txc_isr; address 0x0024 jmp usart1_rxs_isr; address 0x0026 jmp usart1_rxc_isr; address 0x0028 jmp usart1_dre_isr; address 0x002a jmp usart1_txc_isr; address 0x002c jmp usi_start_isr ; address 0x002e jmp usi_ovf_isr ; address 0x0030 jmp twi_isr ; address 0x0032 jmp ee_rdy_isr ; address 0x0034 jmp qtrip_isr ; address 0x0036 reset: ; main program start 49 attiny1634 [preliminary datasheet] 9296c?avr?07/14 external interrupt int0 can be triggered by a falling or rising edge, or a low level. for more information, see section 8.4.1 ?mcucr ? mcu control register? on page 37 . when int0 is enabled and configured as level-triggered, the interrupt triggers as long as the pin is held low. note that detection of falling or rising edge interrupts on int0 requires the presence of an i/o clock as described in section 7. ?clock system? on page 25 . 10.2.1 low level interrupt a low level interrupt on int0 is detected asynchronously. this means that the interrupt source can also be used for waking the part from sleep modes other than idle (the i/o clock is stopped in all sleep modes except idle). note that if a level-triggered interrupt is used for wake-up fr om power-down, the required level must be held long enough for the mcu to complete the wake-up and trigger the level interrupt . if the level disappears before the end of the start-up time, the mcu still wakes up but no interrupt is generated. the start-up time is defined by the sut and cksel fuses as described in section 7. ?clock system? on page 25 . if the low level on the interrupt pin is removed before the de vice has woken up, then program ex ecution is not diverted to the interrupt service routine but continues from the instruction following the ?sleep? command. 10.2.2 pin change interrupt timing a timing example of a pin change interrupt is shown in figure 10-1 . figure 10-1. timing of pin change interrupts clk pin_lat pin_sync pcint(0) pcint_in_(0) pcint_sync pcint_set/flag pcif pin_lat pin_sync pcint_sync clk x 0 clk pcint_set/flag pcint (0) pcmsk(x) pcint (0) pcif pcint_in_(0) le dq attiny1634 [preliminary datasheet] 9296c?avr?07/14 50 10.3 register description 10.3.1 mcucr ? mcu control register bits 1:0 ? isc0[1:0]: interrupt sense control 0 bit 1 and bit 0 external interrupt 0 is triggered by activity on pin int0, provided that the sreg i flag and the corresponding interrupt mask are set. the conditions required to tr igger the interrupt are defined in table 10-2 . note: 1. if low level interrupt is selected, the low level mu st be held until the completion of the currently executing instruction to generate an interrupt. 2. the value on the int0 pin is sampled before detecting edges . if edge or toggle interrupt is selected, pulses that last longer than one clock period generate an interrupt . shorter pulses are not guaranteed to generate an interrupt. 10.3.2 gimsk ? general in terrupt mask register bits 7, 2:0 ? res: reserved bits these bits are reserved and always read as ?0?. bit 6 ? int0: external interrupt request 0 enable the external interrupt for the int0 pin is enabled when this bit and the i bit in the status register (sreg) are set. the trigg er conditions are set with the isc0n bits. activity on the pin causes an interrupt request even if int0 has been configured as an output. bit 5 ? pcie2: pin change interrupt enable 2 when this bit and the i bit of sreg are set, the pin chan ge interrupt 2 is enabled. any change on an enabled pcint[17:12] pin causes a pcint2 interrupt (see table 10-1 on page 47 ). each pin can be individually enabled (see section 10.3.4 ?pcmsk2 ? pin change mask register 2? on page 51 ). bit 4 ? pcie1: pin change interrupt enable 1 when this bit and the i bit of sreg are set, the pin chan ge interrupt 1 is enabled. any change on an enabled pcint[11:8] pin causes a pcint1 interrupt (see table 10-1 on page 47 ). each pin can be individually enabled (see section 10.3.5 ?pcmsk1 ? pin change mask register 1? on page 52 ). bit 76543210 0x36 (0x56) ? sm1 sm0 se ? ? isc01 isc00 mcucr read/write r r/w r/w r/w r r r/w r/w initial value00000000 table 10-2. external interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request (1) . 0 1 any logical change on int0 generates an interrupt request (2) . 1 0 the falling edge of int0 generates an interrupt request (2) . 1 1 the rising edge of int0 generates an interrupt request (2) . bit 76543210 0x3c (0x5c) ? int0 pcie2 pcie1 pcie0 ? ? ? gimsk read/write r r/w r/w r/w r/w r r r initial value00000000 51 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 3 ? pcie0: pin change interrupt enable 0 when this bit and the i bit of sreg are set, the pin change in terrupt 0 is enabled. any change on an enabled pcint[7:0] pin causes a pcint0 interrupt (see table 10-1 on page 47 ). each pin can be individually enabled (see section 10.3.6 ?pcmsk0 ? pin change mask register 0? on page 52 ). 10.3.3 gifr ? general in terrupt flag register bits 7, 2:0 ? res: reserved bits these bits are reserved and always read as ?0?. bit 6 ? intf0: external interrupt flag 0 this bit is set when activity on int0 has triggered an interrupt request. provided that the i bi t in sreg and the int0 bit in gimsk are set, the mcu jumps to th e corresponding interrupt vector. the flag is cleared when the interrupt service routine is execut ed. alternatively, the flag can be cleared by writing a logic o ne to it. this flag is always cleared when int0 is configured as a level interrupt. bit 5 ? pcif2: pin change interrupt flag 2 this bit is set when a logic change on any pcint[17:12] pin has triggered an interrupt request. provided that the i bit in sreg and the pcie2 bit in gimsk are set, the mcu jumps to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alte rnatively, the flag can be cleared by writing a logic one to it . bit 4 ? pcif1: pin change interrupt flag 1 this bit is set when a logic change on any pcint[11:8] pin has tri ggered an interrupt request. prov ided that the i bit in sreg and the pcie1 bit in gimsk are set, the mcu jumps to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alte rnatively, the flag can be cleared by writing a logic one to it . bit 3 ? pcif0: pin change interrupt flag 0 this bit is set when a logic change on any pcint[7:0] pin has tri ggered an interrupt request. provided that the i bit in sreg and the pcie0 bit in gimsk are set, the mcu jumps to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alte rnatively, the flag can be cleared by writing a logic one to it . 10.3.4 pcmsk2 ? pin change mask register 2 bits 7:6 ? res: reserved bits these bits are reserved and always read as ?0?. bits 5:0 ? pcint[17:12]: pin change enable mask 17:12 each pcintn bit selects if the pin chang e interrupt of the corresponding i/o pin is enabled. pin change interrupt on a pin is enabled by setting the mask bit for the pin (pcintn) and the corresponding group bit (pcien) in gimsk. when this bit is cleared, the pin change interrupt on the corresponding pin is disabled. bit 76543210 0x3b (0x5b) ? intf0 pcif2 pcif1 pcif0 ? ? ? gifr read/write r r/w r/w r/w r/w r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 0x29 (0x49) ? ? pcint17 pcint16 pcint15 pcint14 pcint13 pcint12 pcmsk2 read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 52 10.3.5 pcmsk1 ? pin change mask register 1 bits 7:4 ? res: reserved bits these bits are reserved and always read as ?0?. bits 3:0 ? pcint[11:8]: pin change enable mask 11:8 each pcintn bit selects if the pin chang e interrupt of the corresponding i/o pin is enabled. pin change interrupt on a pin is enabled by setting the mask bit for the pin (pcintn) and the corresponding group bit (pcien) in gimsk. when this bit is cleared, the pin change interrupt on the corresponding pin is disabled. 10.3.6 pcmsk0 ? pin change mask register 0 bits 7:0 ? pcint[7:0]: pin change enable mask 7:0 each pcintn bit selects if the pin chang e interrupt of the corresponding i/o pin is enabled. pin change interrupt on a pin is enabled by setting the mask bit for the pin (pcintn) and the corresponding group bit (pcien) in gimsk. when this bit is cleared, the pin change interrupt on the corresponding pin is disabled. bit 7 6 5 4 3 2 1 0 0x28 (0x48) ? ? ? ? pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x27 (0x47) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 53 attiny1634 [preliminary datasheet] 9296c?avr?07/14 11. i/o ports 11.1 overview all avr ? ports have true read-modify- write functionality when used as general digita l i/o ports. this means that the direction of one port pin can be changed without uni ntentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if c onfigured as output) or enabling/di sabling pull-up resistors (if configured as input). most output buffers have symmetrical drive characteristics wi th both high-sink and source capability, while some are asymmetrical and have high-sink and standard so urce capability. the pin driver is strong enough to drive led displays directly. all port pins have individually selectable pull-up resistors with a supply -voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 11-1 on page 53 . for a complete list of parameters, see section 25. ?electrical characteristics? on page 215 . figure 11-1. i/o pin equivalent schematic all registers and bit references in this se ction are written in general form. a lowerc ase ?x? represents the numbering letter f or the port and a lowercase ?n? represents the bit number. however, when using the register or bi t defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in table 11-1 on page 55 . four i/o memory address locations are allocated for each por t, one each for the data register ? portx, data direction register ? ddrx, pull-up enable register ? puex, and the port input pins ? pinx. the port input pins i/o location is read-only, while the data register, the data direct ion register, and the pull-up enable register are read/write. however, writing a logic one to a bit in the pinx register results in a togg le in the corresponding bit in the data register. using the i/o port as a general digital i/o is described in section 11.2 ?ports as a g eneral digital i/o? on page 54 . most port pins are multiplexed with alternate functi ons for the peripheral features on the device. how each alternate function interferes with the port pin is described in section 11.3 ?alternate port functions? on page 59 . see the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect t he use of the other pins in the port as a general digital i/o. c pin r pu pxn logic see figure general digital i/o for details attiny1634 [preliminary datasheet] 9296c?avr?07/14 54 11.2 ports as a general digital i/o the ports are bidirectional i/o po rts with optional internal pull-ups. figure 11-2 shows a functional description of one i/o port pin, here generically called pxn. figure 11-2. general digital i/o (1) note: 1. wex, wrx, wpx, wdx, rex, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , and sleep are common to all ports. d q rrx pxn clr reset synchronizer data bus portxn q q l d q q d q pinxn reset rpx wex: write puex wdx: rrx: wrx: rdx: read ddrx write portx rpx: read portx pin wpx: write pinx register read portx register rex: write ddrx read puex clk i/o : sleep: i/o clock sleep control rdx clk i/o wdx sleep d q clr ddxn q rex reset wex d q clr puexn q wrx wpx 0 1 55 attiny1634 [preliminary datasheet] 9296c?avr?07/14 11.2.1 configuring the pin each port pin consists of four register bits: ddxn, portxn, puexn, a nd pinxn. as shown in section 11.4 ?register description? on page 69 , the ddxn bits are accessed at the ddrx i/o addre ss, the portxn bits at the portx i/o address, the puexn bits at the puex i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects th e direction of this pin. if ddxn is writte n logic one, pxn is configured as an outp ut pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). the pull-up resistor is activated if the puexn is written logic one. to switch the pull-up resistor off, puexn has to be writte n logic zero. table 11-1 summarizes the control signals for the pin value. port pins are tri-stated when a reset condition becomes active, even when no clocks are running. 11.2.2 toggling the pin writing a logic one to pinxn t oggles the value of portxn, regardless of the ddrxn value. note that the sbi instruction can be used to toggle one single bit in a port. 11.2.3 break-before-make switching in break-before-make mode, switching the ddrxn bit from input to output introduces an imm ediate tri-state period lasting one system clock cycle, as indicated in figure 11-3 on page 56 . for example, if t he system clock is 4mhz and the ddrxn is written to make an output, an immediate tri-state period of 250ns is introduced before the value of portxn is seen on the port pin. to avoid glitches it is recommended that the maximum ddrx n toggle frequency is two system clock cycles. the break- before-make mode applies to the entire port and it is activated by the bbmx bit. for more details, see section 11.4.1 ?portcr ? port control register? on page 69 . when switching the ddrxn bit from output to input, no immediat e tri-state period is introduced. table 11-1. port pin configurations ddxn portxn puexn i/o pull-up comment 0 x 0 input no tri-state (hi-z) 0 x 1 input yes draws current if pulled low externally. 1 0 0 output no output low (sink) 1 0 1 output yes not recommended output low (sink) and internal pull-up active. draws current through the intern al pull-up resistor and consumes power constantly. 1 1 0 output no output high (source) 1 1 1 output yes output high (source) and internal pull-up active attiny1634 [preliminary datasheet] 9296c?avr?07/14 56 figure 11-3. switching be tween input and output in break-before-make mode 11.2.4 reading the pin value regardless of the setting of the data direction bit ddxn, the po rt pin can be read through the pinxn register bit. as shown in figure 11-2 on page 54 , the pinxn register bit and the preceding latch co nstitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock; however , this also creates a delay. figure 11-4 shows a timing diagram of the synchronization when re ading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min , respectively. figure 11-4. synchronization when reading an externally applied pin value consider the clock period starting shortl y after the first fallin g edge of the system cl ock. the latch is closed when the clock is low, and goes transparent when the clo ck is high, as indicated by the shaded region of the sync latch signal. the signal value is latched when the system clock goes low. it is clocke d into the pinxn register at the subsequent positive clock edge. as indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin is delayed between ? and 1? system clock periods depending upon the time of assertion. when reading back a software-assigned pin value, a nop (no op eration) instruction must be inserted as indicated in figure 11-5 on page 57 . the out instruction sets the sync latch signal at the positive edge of the clock. in this case, the propagation delay (tpd) through the sync hronizer is one system clock period. system clk instructios r16 portx ddrx r17 px0 px1 0x02 0x01 0x55 intermediate tri-state cycle 0x01 tri state 0x01 tri-state 0x02 tri-state out ddrx, r16 out ddrx, r17 nop intermediate tri-state cycle system clk instructios sync latch pinxn r17 xxx xxx 0x00 0xff in r17, pinx t pd, max t pd, min 57 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 11-5. synchronization when reading a software-assigned pin value 11.2.5 digital input enable and sleep modes as shown in figure 11-2 on page 54 , the digital input signal can be clamped to gr ound at the input of th e schmitt trigger. the signal denoted sleep in the figure is set by the mcu sleep controller in power-down and standby modes to avoid high power consumption if some input signals are left floating or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrupt pins. if the external interrupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in section 11.3 ?alternate port functions? on page 59 . if a logic high level (?1?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falli ng edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding exte rnal interrupt flag is set when resuming from the above-mentioned sleep mode because the clamping in this sleep mode produces the requested logic change. 11.2.6 unconnected pins if some pins are unused, atmel recommends ensuring these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, fl oating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (reset, active mode, and idle mode). the simplest method to ensure a defined level for an unused pin is to enable the internal pull-up. in this case, the pull-up is disabled during reset. if low power consumption during reset is important, it is advisable to use an external pull-up or pull-down. connecting unused pins directly to v cc or gnd is not recommended because this may cause excessive currents if the pin is accidentally configured as an output. t pd 0xff 0xff 0x00 nop in r17, pinx out portx, r16 instructions sync latch r16 r17 pinxn system clk attiny1634 [preliminary datasheet] 9296c?avr?07/14 58 11.2.7 program examples the following code example shows how to set port a pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as inputs with a pull-up assigned to port pin 4. the resulting pin values are read back again, but as previously discussed, an nop instruction is included to be able to read back the value recently assigned to some of the pins. note: two temporary registers are used to minimize the time from when pull-ups are set on pins 0, 1, and 4 until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. note: see section 4.2 ?code examples? on page 7 . assembly code example ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< attiny1634 [preliminary datasheet] 9296c?avr?07/14 60 the illustration in the figure above serves as a gen eric description applicable to all port pins in the avr ? microcontroller family. some overriding signals may not be present in all port pins. table 11-2 summarizes the function of the overridi ng signals. the pin and port indexes from figure 11-6 are not shown in the subsequent tables. the overriding signals are generated in ternally in the modules having the alternate function. the following subsections briefly describe the alternate functi ons for each port and indicate the overriding signals to the alternate function. for more information, see the alternate function description. table 11-2. generic description of overri ding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when puexn = 0b1. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the puexn register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output dr iver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the se tting of the ddxn register bit. pvoe port value override enable if this signal is set and the output dr iver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital i nput enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the m cu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure the signal is connected to the output of the schmit t trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function uses its own synchronizer. aio analog input/output this is the analog input/output to/fro m alternate functions. the signal is connected directly to the pad and can be used bidirectionally. 61 attiny1634 [preliminary datasheet] 9296c?avr?07/14 11.3.1 alternate functions of port a the port a pins with alternate function are shown in table 11-3 . port a, bit 0 ? aref/pcint0 aref: external analog reference for adc. the pull-up and output driver are disabled on pa0 when the pin is used as an external reference or internal voltage reference with an external capacitor at the aref pin. pcint0: pin change interrupt source 0. the pa0 pin can serv e as an external interrupt source for pin change interrupt 0. port a, bit 1 ? ain0/pcint1 ain0: analog comparator positive input. configure the port pin as input with the internal pull-up switched off to keep the digital port function from interfering with the function of the analog comparator. pcint1: pin change interrupt source 1. the pa1 pin can serv e as an external interrupt source for pin change interrupt 0. port a, bit 2 ? ain1/pcint2 ain1: analog comparator negative input. configure the port pin as input with the internal pull-up switched off to keep the digital port function from interfering with the function of the analog comparator. pcint2: pin change interrupt source 2. the pa2 pin can serv e as an external interrupt source for pin change interrupt 0. table 11-3. port a pins alternate functions port pin alternate function pa0 aref: external analog reference pcint0: pin change interrupt 0, source 0 pa1 ain0: analog comparator, positive input pcint1: pin change interrupt 0, source 1 pa2 ain1: analog comparator, negative input pcint2: pin change interrupt 0, source 2 pa3 adc0: adc input channel 0 sns: sense line for capacitive measurement t1: timer/counter1 clock source pcint3: pin change interrupt 0, source 3 pa4 adc1: adc input channel 1 t0: timer/counter0 clock source pcint4: pin change interrupt 0, source 4 pa5 adc2: adc input channel 2 oc0b: timer/counter0 compare match b output pcint5: pin change interrupt 0, source 5 pa6 adc3: adc input channel 3 oc1b: timer/counter1 compare match b output pcint6: pin change interrupt 0, source 6 pa7 adc4: adc input channel 4 rxd0: uart0 data receiver pcint7: pin change interrupt 0, source 7 attiny1634 [preliminary datasheet] 9296c?avr?07/14 62 port a, bit 3 ? adc0/t1/pcint3 adc0: analog to digital converter, channel 0. sns: sense line for capacitive measurement using qtouch technology. connected to c s . t1: timer/counter1 counter source. pcint3: pin change interrupt source 3. the pa3 pin can serv e as an external interrupt source for pin change interrupt 0. port a, bit 4 ? adc1/t0/pcint4 adc1: analog to digital converter, channel 1. t0: timer/counter0 counter source. pcint4: pin change interrupt source 4. the pa4 pin can serve as an external interrupt source for pin change interrupt 0. port a, bit 5 ? adc2/oc0b/pcint5 adc2: analog to digital converter, channel 2. oc0b: output compare match output. the pa5 pin can serv e as an external output for the timer/counter0 compare match b. the pa5 pin has to be configured as an output (dda5 set (?1?)) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. pcint5: pin change interrupt source 5. the pa5 pin can serv e as an external interrupt source for pin change interrupt 0. port a, bit 6 ? adc3/oc1b/pcint6 adc3: analog to digital converter, channel 3. oc1b: output compare match output. the pa6 pin can serv e as an external output for the timer/counter1 compare match b. the pin has to be c onfigured as an output (dda6 set (?1?)) to serve this function. this is also the output pin for the pwm mode timer function. pcint6: pin change interrupt source 6. the pa6 pin can serv e as an external interrupt source for pin change interrupt 0. port a, bit 7 ? adc4/rxd0/pcint7 adc4: analog to digital converter, channel 4. rxd0: uart0 data receiver. pcint7: pin change interrupt source 7. the pa7 pin can serv e as an external interrupt source for pin change interrupt 0. 63 attiny1634 [preliminary datasheet] 9296c?avr?07/14 table 11-4 and table 11-6 compares the alternate functions of po rt a to the overriding signals shown in figure 11-6 on page 59 . table 11-4. overriding signals for alternate functions in pa[7:5] signal name pa7/adc4/rxd0/pcint7 pa6/adc3/oc1b/pcint6 pa5/adc2/oc0b/pcint5 puoe rxd0_oe 0 0 puov puea7 0 0 ddoe rxd0_en 0 0 ddov 0 0 0 pvoe 0 oc1b enable oc0b enable pvov 0 oc1b oc0b ptoe 0 0 0 dieoe (pcint7 ? pcie0) + adc4d (pcint6 ? pcie0) + adc3d (pcint5 ? pcie) + adc2d dieov pcint7 ? pcie0 pcint6 ? pcie0 pcint5 ? pcie0 di rxd0/pcint7 input pcint6 input pcint5 input aio adc4 input adc3 input adc2 input table 11-5. overriding signals for alternate functions in pa[4:2] signal name pa4/adc1/t0/pcint4 pa3/adc0/sns/t1/pcint3 pa2/ain1/pcint2 puoe 0 0 0 puov 0 0 0 ddoe 0 0 0 ddov 0 0 0 pvoe 0 0 0 pvov 0 0 0 ptoe 0 0 0 dieoe (pcint4 ? pcie0) + adc1d (pcint3 ? pcie0) + adc0d (pcint2 ? pci0) + ain1d dieov pcint4 ? pcie0 pcint3 ? pcie0 pcint2 ? pcie0 di t0/pcint4 input t1/pcint3 input pcint2 input aio adc1 input adc0 or sns input analog comparator negative input table 11-6. overriding signals for alternate functions in pa[1:0] signal name pa1/ain0/pcint1 pa0/aref/pcint0 puoe 0 reset ? (refs1 ? refs0 + refs1 ? refs0) puov 0 0 ddoe 0 reset ? (refs1 ? refs0 + refs1 ? refs0) ddov 0 0 pvoe 0 reset ? (refs1 ? refs0 + refs1 ? refs0) pvov 0 0 ptoe 0 0 dieoe (pcint1 ? pcie0) + ain0d (pcint0 ? pcie0) + arefd dieov pcint1 ? pcie0 pcint0 ? pcie0 di pcint1 input pcint0 input aio analog comparator positive input analog reference attiny1634 [preliminary datasheet] 9296c?avr?07/14 64 11.3.2 alternate functions of port b the port b pins with alternate function are shown in table 11-7 . port b, bit 0 ? adc5/txd0/pcint8 adc5: analog to digital converter, channel 5. txd0: uart0 data transmitter. pcint8: pin change interrupt source 8. the pb0 pin can serve as an external interrupt source for pin change interrupt 1. port b, bit 1 ? adc6/rxd1/di/sda/pcint9 adc6: analog to digital converter, channel 6. rxd1: uart1 data receiver. di: data input in usi three-wire mode. usi three-wire mode does not override normal port functions. the pin must therefore be configured as an input for the di function. sda: two-wire mode serial interface data. pcint9: pin change interrupt source 9. the pb1 pin can serve as an external interrupt source for pin change interrupt 1. port b, bit 2 ? adc7/txd1/do/pcint10 adc7: analog to digital converter, channel 7. txd1: uart1 data transmitter. do: data output in usi three-wire mode. data output (do) overrides the portb2 value and is driven to the port when the data direction bit ddb2 is set (?1?). however the portb2 bit still controls the pull-up, enabling pull-up if the direction is input and portb2 is set (?1?). pcint10: pin change interrupt source 10. the pb2 pin can serve as an external interrupt source for pin change interrupt 1. port b, bit 3 ? adc8/oc1a/pcint11 adc8: analog to digital converter, channel 8. oc1a: output compare match output. the pb3 pin can serve as an external output for the timer/counter1 compare match a. the pin has to be c onfigured as an output (ddb3 set (?1?)) to serve this function. this is also the output pin for the pwm mode timer function. pcint11: pin change interrupt source 11. the pb3 pin can serve as an external interrupt source for pin change interrupt 1. table 11-7. port b pins alternate functions port pin alternate function pb0 adc5: adc input channel 5 txd0: uart0 data transmitter pcint8: pin change interrupt 1, source 8 pb1 adc6: adc input channel 6 rxd1: uart1 data receiver di: usi data input (three-wire mode) sda: usi data input (two-wire mode) pcint9: pin change interrupt 1, source 9 pb2 adc7: adc input channel 7 txd1: uart1 data transmitter do: usi data output (three-wire mode) pcint10: pin change interrupt 1, source 10 pb3 adc8: adc input channel 8 oc1a: timer/counter1 compare match a output pcint11: pin change interrupt 1, source 11 65 attiny1634 [preliminary datasheet] 9296c?avr?07/14 table 11-8 on page 65 and table 11-9 on page 65 compare the alternate functions of port b to the overriding signals shown in figure 11-6 on page 59 . table 11-8. overriding signals for alternate functions in pb[3:2] signal name pb3/adc8/oc1a/pcint11 pb2/adc7/txd1/do/pcint10 puoe 0 txd1_oe puov 0 0 ddoe 0 txd1_oe ddov 0 0 pvoe oc1a enable txd1_oe + usi_three_wire pvov oc1a (txd1_oe ? txd_pvov) + (txd1_oe ? do) ptoe 0 0 dieoe pcint11 ? pcie1 + adc8d pcint10 ? pcie1 + adc7d dieov pcint11 ? pcie1 pcint10 ? pcie1 + int0 di pcint11 input pcint10 input aio adc8 input adc7 input table 11-9. overriding signals for alternate functions in pb[1:0] signal name pb1/adc5/rxd1/di/sda/pcint9 pb0/adc4/txd0/pcint8 puoe rxd1_oe txd0_oe puov pueb1 0 ddoe rxd1_en + usi_two_wire txd0_oe ddov rxd1_en ) ? (sda + portb1 ) ? ddb1 pvoe rxd1_en ) ? usi_two_wire ? ddb1 txd0_oe pvov 0 txd0_pvov ptoe 0 0 dieoe usisie + (pcint9 ? pcie1) + adc6d (pcint8 ? pcie1) + adc5d dieov usisie + (pcint9 ? pcie1) pcint8 ? pcie1 di rxd1/di/sda/pcint9 input pcint8 input aio adc6 input adc5 input attiny1634 [preliminary datasheet] 9296c?avr?07/14 66 11.3.3 alternate functions of port c the port c pins with alte rnate function are shown in table 11-7 . port c, bit 0 ? adc9/xck0/oc0a/pcint12 adc9: analog to digital converter, channel 9. xck0: usart0 transfer clock used by synchronous transfer mode only. oc0a: output compare match output. the pc0 pin can serv e as an external output for the timer/counter0 compare match a. the pc0 pin has to be configured as an output (ddc0 set (?1?)) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. pcint12: pin change interrupt source 12. the pc0 pin can serve as an external interrupt source for pin change interrupt 1. port c, bit 1 ? adc10/x ck1/usck/scl/icp1/pcint13 adc10: analog to digital converter, channel 10. xck1: usart1 transfer clock used only by synchronous transfer mode. usck: three-wire mode universal serial interface clock. scl: two-wire mode serial clock for usi two-wire mode. icp1: input capture pin. the pc1 pin can ac t as an input capture pin for timer/counter1. pcint13: pin change interrupt source 13. the pc1 pin can serve as an external interrupt source for pin change interrupt 1. table 11-10. port c pins alternate functions port pin alternate function pc0 adc9: adc input channel 9 xck0: usart 0 transfer clock (synchronous mode) oc0a: timer/counter0 compare match a output pcint12: pin change interrupt 2, source 12 pc1 adc10: adc input channel 10 xck1: usart 1 transfer clock (synchronous mode) usck: usi clock (three-wire mode) scl: usi clock (two-wire mode) icp1: timer/counter1 input capture pin pcint13: pin change interrupt 2, source 13 pc2 adc11: adc input channel 11 int0: external interrupt 0 input clko: system clock output pcint14: pin change interrupt 2, source 14 pc3 reset : reset pin dw: debugwire i/o pcint15: pin change interrupt 2, source 15 pc4 xtal2: crystal oscillator output pcint16: pin change interrupt 2, source 16 pc5 xtal1: crystal oscillator input clki: external clock input pcint17: pin change interrupt 2, source 17 67 attiny1634 [preliminary datasheet] 9296c?avr?07/14 port c, bit 2 ? adc11/int0/clko/pcint14 adc11: analog to digital converter, channel 11. int0: external interrupt request 0. clko: system clock output. the system clock can be output on the pc2 pin. th e system clock is output if the ckout fuse is programmed, regardless of the portc2 and ddc2 settings. it is also output during reset. pcint14: pin change interrupt source 14. the pc2 pin can serve as an external interrupt source for pin change interrupt 1. port c, bit 3 ? reset /dw/pcint15 reset : external reset input is active low and enabled by unprogramming (?1?) the rstdisbl fuse. pull-up is activated and output driver and digital input ar e deactivated when the pin is used as the reset pin. dw: when the debugwire enable (dwen) fuse is progra mmed and lock bits are unprogrammed, the debugwire system within the target device is ac tivated. the reset port pin is conf igured as a wire-and (open-drain) bidrectional i/o pin with pull-up enabled and becomes the communication gateway be tween target and emulator. pcint15: pin change interrupt source 15. the pc3 pin can serve as an external interrupt source for pin change interrupt 1. port c, bit 4 ? xtal2/pcint16 xtal2: chip clock oscillator pin 2. used as clock pin for all chip clock sources except inte rnal calibrated oscillator and external clock. when used as a clock pin, the pin cannot be used as an i/o pin. when using internal calibrated oscillator as a chip clock source, pc4 serves as an ordinary i/o pin. pcint16: pin change interrupt source 16. the pc4 pin can serve as an external interrupt source for pin change interrupt 1. port c, bit 5 ? xtal1/clki/pcint17 xtal1: chip clock oscillator pin 1. used for all chip clo ck sources except internal calibrated oscillator. when used as a clock pin, the pin cannot be used as an i/o pin. when using internal calibrated oscillator as a chip clock source, pc5 serves as an ordinary i/o pin. clki: clock input from an external clock source (see section 7.2.1 ?external clock? on page 26 ). pcint17: pin change interrupt source 17. the pc5 pin can serve as an external interrupt source for pin change interrupt 1. attiny1634 [preliminary datasheet] 9296c?avr?07/14 68 table 11-4 and table 11-6 compares the alternate functions of po rt a to the overriding signals shown in figure 11-6 on page 59 . notes: 1. ext_clock = external clo ck is selected as system clock. 2. ext_osc = crystal oscillator or low frequency crystal oscillato r is selected as system clock. 3. rstdisbl is ?1? when the fuse is ?0? (programmed). 4. debugwire is enabled when the dwen fuse is programmed and lock bits are unprogrammed. table 11-11. overriding signals for alternate functions in pc[5:3] signal name pc5/xtal1/clki/pcint17 pc4/xtal2/ pcint16 pc3/reset /dw/ pcint15 puoe ext_clock (1) + ext_osc (2) ext_osc (2) rstdisbl (3) + debugwire_enable (4) puov 0 0 1 ddoe ext_clock (1) + ext_osc (2) ext_osc (2) rstdisbl (3) + debugwire_enable (4) ddov 0 0 debugwire_enable (4) ? debugwire transmit pvoe ext_clock (1) + ext_osc (2) ext_osc (2) rstdisbl (3) + debugwire_enable (4) pvov 0 0 0 ptoe 0 0 0 dieoe ext_clock (1) + ext_osc (2) + (pcint17 ? pcie2) ext_osc (2) + pcint16 ? pcie2 rstdisbl (3) + debugwire_enable (4) + pcint15 ? pcie2 dieov (ext_clock (1) ? pwr_down ) + (ext_clock (1) ? ext_clock (1) ? pcint17 ? pcie2) ext_osc (2) ? pcint16 ? pcie2 debugwire_enable (4) + (rstdisbl (3) ? pcint15 ? pcie2) di clock/pcint17 input pcint16 input dw/pcint15 input aio xtal1 xtal2 table 11-12. overriding signals for alternate functions in pc[2:0] signal name pc2/adc11/int0/clko/ pcint14 pc1/adc10/xck1/usck/ scl/icp1/pcint13 pc0/adc9/xck0/ oc0a/pcint12 puoe ckout_io usi_two_wire 0 puov 0 0 0 ddoe ckout_io usi_two_wire 0 ddov 1 (usi_scl_hold + portc1 ) ? ddc1 0 pvoe ckout_io xcko1_pvoe + usi_two_wire ? ddc1 xcko0_pvoe + oc0a enable pvov ckout_io ? system clock xcko1_pvov xcko0_pvov + oc0a ptoe 0 usi_ptoe 0 dieoe int0 + (pcint14 ? pcie2) + adc11d xck1 input enable + usisie + (pcint13 ? pcie2) + adc10d xck0 input enable + (pcint12 ? pcie2) + adc9d dieov int0 + (pcint14 ? pcie2) usisie + (pcint13 ? pcie2) pcint12 ? pcie2 di int0/pcint14 input xck1/usck/scl/icp1/ pcint13 input xck0/pcint12 input aio adc11 input adc10 input adc9 input 69 attiny1634 [preliminary datasheet] 9296c?avr?07/14 11.4 register description 11.4.1 portcr ? port control register bits 7:3 ? res: reserved bits these bits are reserved and always read as ?0?. bit 2 ? bbmc: break-before-make mode enable when this bit is set, the break-before-make mode is activated for the entire port c. the intermediate tri- state cycle is then inserted when writing ddrcn to make an output. for further information, see section 11.2.3 ?break-before-make switching? on page 55 . bit 1 ? bbmb: break-before-make mode enable when this bit is set, the brea k-before-make mode is activated for the entire port b. the inte rmediate tri-state cycle is then inserted when writing ddrbn to make an output. for further information, see section 11.2.3 ?break-before-make switching? on page 55 . bit 0 ? bbma: break-before-make mode enable when this bit is set, the brea k-before-make mode is activated for the entire port a. the inte rmediate tri-state cycle is then inserted when writing ddran to make an output. for further information, see section 11.2.3 ?break-before-make switching? on page 55 . 11.4.2 puea ? port a pull-up enable control register 11.4.3 porta ? port a data register 11.4.4 ddra ? port a data direction register bit 7 6 5 4 3 2 1 0 0x13 (0x33) ? ? ? ? ? bbmc bbmb bbma portcr read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x12 (0x32) puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 puea read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x11 (0x31) porta7 porta6 porta5 porta4 port a3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x10 (0x30) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 70 11.4.5 pina ? port a input pins 11.4.6 pueb ? port b pull-up enable control register 11.4.7 portb ? port b data register 11.4.8 ddrb ? port b data direction register 11.4.9 pinb ? port b input pins 11.4.10 puec ? port c pull-up enable control register 11.4.11 portc ? port c data register bit 76543210 0x0f (0x2f) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x0e (0x2e) ? ? ? ? pueb3 pueb2 pueb1 pueb0 pueb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0d (0x2d) ? ? ? ? portb3 portb2 portb1 portb0 portb read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 0x0c (0x2c) ? ? ? ? ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 0x0b (0x2b) ? ? ? ? pinb3 pinb2 pinb1 pinb0 pinb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 n/a n/a n/a n/a bit 76543210 0x0a (0x2a) ? ? puec5 puec4 puec3 puec2 puec1 puec0 puec read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x09 (0x29) ? ? portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 71 attiny1634 [preliminary datasheet] 9296c?avr?07/14 11.4.12 ddrc ? port c data direction register 11.4.13 pinc ? port c input pins bit 76543210 0x08 (0x28) ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x07 (0x27) ? ? pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 n/a n/a n/a n/a n/a n/a attiny1634 [preliminary datasheet] 9296c?avr?07/14 72 12. 8-bit timer/counter0 with pwm 12.1 features two independent output compare units double-buffered output compare registers clear timer on compare match (auto reload) glitch-free phase-correct pul se width modulator (pwm) variable pwm period frequency generator three independent interrupt sources (tov0, ocf0a, and ocf0b) 12.2 overview timer/counter0 is a general purpose 8-bit timer/counter mo dule with two independent output compare units and pwm support. it allows accurate program execution timing (event management ) and wave generation. a simplified block diagram of the 8-bit timer/counter is shown in figure 12-1 . for the specific plac ement of i/o pins, see figure 1-1 on page 3 . cpu-accessible i/o registers, including i/o bits a nd i/o pins are shown in bold. the device-specific i/o register and bit locations are listed in section 12.9 ?register description? on page 82 . figure 12-1. 8-bit timer/counter block diagram tcntn timer/counter count clear direction ocrna ocrnb tccrna tccrnb = top bottom ocna (int. req.) waveform generation fixed top value data bus = = = 0 ocna ocnb (int. req.) waveform generation ocnb control logic clk tn tovn (int. req.) edge detector (from prescaler) clock select tn 73 attiny1634 [preliminary datasheet] 9296c?avr?07/14 12.2.1 registers the timer/counter (tcnt0) and output compare registers (o cr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated as ?int.req.? in figure 12-1 ) signals are all visible in the timer interr upt flag register (tifr). all interrupts are individually masked with the timer inte rrupt mask register (timsk). tifr a nd timsk are not shown in figure 2-1. the timer/counter can be clocked internally via the prescaler or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/ counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t0 ). the double-buffered output compare r egisters (ocr0a and ocr0b) are compar ed with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b) (for more information, see section 12.5 ?output compare unit? on page 74 ). the compare match event also sets the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 12.2.2 definitions many register and bit references in this section are writte n in general form. a lowercase ?n? replaces the timer/counter number, in this case 0. a lowercase ?x? replaces the output co mpare unit, in this case compar e unit a or compare unit b. however, when using the register or bit defines in a progr am, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value, etc. the definitions in table 12-1 are also used extensively throughout the document. 12.3 clock sources the timer/counter can be clocked by an internal or an extern al clock source. the clock sour ce is selected by the clock select logic which is controlled by the cl ock select (cs0[2:0]) bits located in the timer/counter control register (tccr0b). for details on clock sources and prescaler, see section 14. ?timer/counter prescaler? on page 112 . 12.4 counter unit the main part of the 8-bit timer/counter is the programmable bidirectional counter unit. figure 12-2 shows a block diagram of the counter and its surroundings. figure 12-2. counter unit block diagram table 12-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment depends on the operating mode. top bottom tovn (int. req.) data bus control logic tcntn clk tn count clear direction edge detector (from prescaler) clock select tn attiny1634 [preliminary datasheet] 9296c?avr?07/14 74 signal description (internal signals): count increment or decrement tcnt0 by 1 direction select between increment and decrement clear clear tcnt0 (set all bits to ?0?) clk t n timer/counter clock, referred to as clk t0 in the following top indicates that tcnt0 has reached maximum value bottom indicates that tcnt0 has reached minimum value (?0?) depending on the operating mode used, the counter is cleared, incremented, or decrement ed at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bi ts (cs0[2:0]). when no clock source is selected (cs0[2:0] = 0), the ti mer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has pr iority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are close connections between how the counter behaves (counts) and ho w waveforms are generated on the output compare output oc0a. for more details about advanced counting sequences and waveform generation, see section 12.7 ?operating modes? on page 76 . the timer/counter overflow flag (tov0) is set according to the operating mode selected by the wgm0[1:0] bits. tov0 can be used for generating a cpu interrupt. 12.5 output compare unit the 8-bit comparator continuously com pares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a ma tch. a match sets the output compare flag (ocf0a or ocf0b) at the next timer clo ck cycle. if the corresponding interrupt is enabled , the output compare fl ag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared via software by writing a logic one to its i/o bit location. the waveform generator uses the match signal to generate an output according to the operating mode set by t he wgm0[2:0] bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generato r for handling the special cases of the extreme values in some operating modes (see section 12.7 ?operating modes? on page 76 ). figure 12-3 shows a block diagram of the output compare unit. figure 12-3. output comp are unit, block diagram ocfnx (int. req.) = (8-bit comparator) ocrnx waveform generator tcntn ocnx top bottom focn wgmn[1:0] comnx[1:0] data bus 75 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the ocr0x registers are double-buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) operating modes, double-buffering is disabled. the double-buffering synchronizes the update of the ocr0x compare registers to either the top or bott om of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pul ses, thus making the output glitch-free. the ocr0x register access may seem complex, but this is no t the case. when the double-buffering is enabled, the cpu has access to the ocr0x buffer register and if double-bufferi ng is disabled, the cpu accesses the ocr0x directly. 12.5.1 force output compare in non-pwm waveform generation modes the match output of the comparator can be forced by writing a ?1? to the force output compare (0x) bit. forcing compare ma tch does not set the ocf0x flag or reload /clear the timer, but the oc0x pin is updated as if a real compare match had o ccurred (the com0x[1:0] bits settings define whether the oc0x pin is set, cleared or toggled). 12.5.2 compare match blocking by tcnt0 write all cpu write operations to th e tcnt0 register block any com pare match that occurs in the next timer clock cycle even when the timer is stopped. this feature allows ocr0x to be initia lized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 12.5.3 using the ou tput compare unit because writing tcnt0 in any operating mode blocks all compare matches for one timer clock cycle, risks arise from changing tcnt0 while using the output compare unit, regardless of whether the timer/counter is r unning or not. if the value written to tcnt0 equals the ocr0x valu e, the compare match is missed, result ing in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is down-counting. the setup of the oc0x should be performed bef ore setting the data direction register for the port pin to output. the easiest way to set the oc0x value is to use the force output compare (0x) strobe bits in normal mode. the oc0x registers retain their values even when changing between waveform generation modes. be aware that the com0x[1:0] bits are not double-buffered toge ther with the compare value. changing the com0x[1:0] bits takes effect immediately. 12.6 compare match output unit the compare output mode (com0x[1:0]) bi ts have two functions. the waveform ge nerator uses the com0x[1:0] bits for defining the output compar e (oc0x) state at the next compare match. also, the com0x[1:0] bits cont rol the oc0x pin output source. figure 12-4 on page 76 shows a simplified schematic of the logic a ffected by the com0x[1:0] bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bol d. only the parts of the general i/o port control registers (dd r and port) affected by the com0x[1:0] bits are displayed. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occurs, the oc0x r egister is reset to ?0?. attiny1634 [preliminary datasheet] 9296c?avr?07/14 76 figure 12-4. compare match output unit, schematic the general i/o port function is overridden by the output co mpare (oc0x) from the waveform generator if either of the com0x[1:0] bits are set. however, the oc 0x pin direction (input or output) is st ill controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as the output before the oc0x value is visible on the pin. the port overri de function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the output is enabled. note that some com0x[1:0] bit settings are reserv ed for certain operating modes (see section 12.9 ?register description? on page 82 ). 12.6.1 compare output mode and waveform generation the waveform generator uses the com0x[1:0] bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x[1:0] = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes, see table 12-2 on page 82 . for fast pwm mode, see table 12- 3 on page 82 and for phase correct pwm, see table 12-4 on page 82 . a change in the com0x[1:0] bits state ha s an effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the 0x strobe bits. 12.7 operating modes the operating modes, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm0[2:0]) and compare output mode (com0x[1:0]) bits. the compare output mode bits do not affect the counting sequence while the waveform generati on mode bits do. the com0x[1:0] bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes, the com0x[1:0] bits control whether the output should be se t, cleared, or toggled at a compare match (see section 12.7 ?operating modes? on page 76 ). for detailed timing information, see figure 12-8 on page 80 , figure 12-9 on page 80 , figure 12-10 on page 81 , and figure 12-11 on page 81 in section 12.8 ?timer/counter timing diagrams? on page 80 . data bus 0 1 q d comnx1 comnx0 focn ocnx waveform generator q d port q d ddr ocnx pin clk i/o 77 attiny1634 [preliminary datasheet] 9296c?avr?07/14 12.7.1 normal mode the simplest operating mode is the normal mode (wgm0[2:0] = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the coun ter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in norma l operation the timer/counter overflow flag (tov0) is set in the same timer clock cycle when the tcnt 0 becomes ?0?. the tov0 flag in this case behaves as a ninth bit, except that it is only set, not cleared. however, combined with the timer ov erflow interrupt that automatic ally clears the tov0 flag, the timer resolution can be increased by software. there are no s pecial cases to consider in normal mode; a new counter value can be written at any time. the output compare unit can be used to generate interrupts at a given time. using the output compare to generate waveforms in normal mode is not recommended because this occupies too much cpu time. 12.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (w gm0[2:0] = 2) the ocr0a register is us ed to manipulate the counter resolution. in ctc mode the counter is cleared to ?0? when the counter value (tcnt0) matc hes the ocr0a. the ocr0a defines the top value for the counter and therefore its resolution as well. this mode allows greater contro l of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 12-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 12-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reac hes the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updat ing the top value. however, changing top to a value close to bottom when the counter is running with no prescaler value or a low prescaler value must be done with care because the ctc mode does not have the double-buffering feature. if the new value written to oc r0a is lower than the current value of tcnt0, the counter misses the compare ma tch. the counter then has to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mo de, the oc0a output can be set to toggle its logic level on each compare match by setting the compare output mode bits to toggle mode (com0a[1:0] = 1). the oc0a value is not visible on the port pin unless the data direction for the pin is set to output. the waveform generated has a maximum frequency of 0 = f clk_i/o /2 when ocr0a is set to ?0? (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale fa ctor (1, 8, 64, 256, or 1024). as for normal operating mode, the tov0 flag is set in the same timer clock cycle in which t he counter counts from max to 0x00. 12 tcntn (comnx[1:0] = 1) ocnx (toggle) period 3 ocnx interrupt flag set 4 f ocnx f clk_i/o 2n 1 ocrnx + () ---------------------------------------------------- = attiny1634 [preliminary datasheet] 9296c?avr?07/14 78 12.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm0[ 2:0] = 3 or 7) provides a high-frequency pwm waveform generation option. the fast pwm differs from the other pwm optio n by its single-slope operation. the counter counts from bottom to top, then restarts fr om bottom. top is defined as 0xff when wgm0[2:0] = 3, and ocr0a when wgm0[2:0] = 7. in non-inverting compare output mode th e output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bo ttom. in inverting compare output mode the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fa st pwm mode can be two times higher than the phase correct pwm mode that uses dual-s lope operation. a high frequen cy makes the fast pwm mode highly suitable for power regulation, rectification, and da c applications and also allows external components (coils, capacitors) of small physical size, thus reducing overall system cost. in fast pwm mode the counter is incremented until the counte r value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode can be seen in figure 12-6 on page 78 . the tcnt0 value is shown in the timing diagram as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 12-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the co unter reaches top. if the inte rrupt is enabled, the interrupt handler routine can be used fo r updating the compare value. in fast pwm mode the compare unit allows generation of pwm waveforms on the oc0x pins. se tting the com0x[1:0] bits to ?2? produces a non-inverted pwm and an inverted pwm output ca n be generated by setting the com0x[1:0] to ?3?. setting the com0a[1:0] bits to ?1? allows the oc0a pin to toggle on compare matches if the wgm02 bi t is set. this option is not available for the oc0b pin (see table 12-3 on page 82 ). the actual oc0x value is only visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0. the counter is cleared (changes from top to bottom) by clearing (or setting) the oc0x register at the timer clock cycle. the pwm frequency for the output can be calculated with this equation: the n variable represents the prescale fa ctor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output is a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max results in a constantly high or low output (depending on the polarity of the output set by the com0a[1:0] bits.) 1234567 tcntn (comnx[1:0] = 2) (comnx[1:0] = 3) ocnx ocnx period ocrnx update and tovn interrupt flag set ocrnx interrupt flag set f ocnxpwm f clk_i/o n 256 ------------------- = 79 attiny1634 [preliminary datasheet] 9296c?avr?07/14 a frequency (with 50% duty cycle) waveform output in fast pw m mode can be achieved by setting oc0x to toggle its logic level on each compare match (com0x[1:0] = 1). t he waveform generated has a maximum frequency of 0 = f clk_i/o /2 when ocr0a is set to ?0?. this feature is similar to the oc0a t oggle in ctc mode except the double -buffer feature of the output compare unit is enabled in the fast pwm mode. 12.7.4 phase correct pwm mode the phase correct pwm mode (wgm0[2:0] = 1 or 5) provides a high-resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter count s repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when wgm0[2:0] = 1, and ocr0a when wgm0[2:0] = 5. in non-inverting compare output mode the out put compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while up-counting and set on the compare match while down-counting. in inverting output compare mode the operation is inverted. the dual-slope operation has lowe r maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slo pe pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt0 value is equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode can be seen in figure 12-7 on page 79 . the tcnt0 value is shown in the timing diagram as a histogram to illustrate the dual-slope o peration. the diagram includes non-inver ted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes repr esent compare matches between ocr0x and tcnt0. figure 12-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode the compare unit allows genera tion of pwm waveforms on the oc0x pins. setting the com0x[1:0] bits to ?2? produces a non-inv erted pwm. an inverted pw m output can be generated by setting the com0x[1:0] to ?3?: setting the com0a0 bits to ?1? allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 12-4 on page 82 ). the actual oc0x value is only visible on the port pin if the data direction for the port pin is set as output. the pwm wa veform is generated by clearing (o r setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the coun ter decrements. when using pha se correct pwm, the pwm frequency for the output can be calculated with this equation: the n variable represents the prescale fa ctor (1, 8, 64, 256, or 1024). 123 tcntn (comnx[1:0] = 2) (comnx[1:0] = 3) ocnx ocnx period tovn interrupt flag set ocrnx update ocnx interrupt flag set f ocnxpcpwm f clk_i/o n510 ------------------- = attiny1634 [preliminary datasheet] 9296c?avr?07/14 80 the extreme values for the ocr0a regist er represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the out put is continuously low and if set equal to max the output is continuously high for non-inverted pwm mode. for inverted pwm, the output ha s the opposite logic values. at the very start of period 2 in figure 12-7 on page 79 ocn has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry ar ound bottom. there are two cases that result in a transition without a compare match. ocr0a changes its value from max as shown in figure 12-7 on page 79 . when the ocr0a value is max, the ocn pin value is the same as the result of a down-countin g compare match. to ensure symmetry around bottom, the ocn value at max must correspond to the result of an up-counting compare match. the timer starts counting from a value higher than the one in ocr0a, thus missing th e compare match and hence the ocn change that would have happened on the way up. 12.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include inform ation on when interrupt flags are set. figure 12-8 contains timing data for basic timer/counter operation. the figure show s the count sequence close to the max value in all modes other than phase correct pwm mode. figure 12-8. timer/counter timi ng diagram, no prescaling figure 12-9 shows the same timing data, but with the prescaler enabled. figure 12-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) max - 1 clk i/o (clk i/o /1) tcntn tovn clk tn max bottom bottom + 1 max - 1 clk i/o (clk i/o /8) tcntn tovn clk tn max bottom bottom + 1 81 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 12-10 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode where ocr0a is top. figure 12-10.timer/counter timing diagra m, setting of ocf0x, with prescaler (f clk_i/o /8) figure 12-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 12-11.timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2 top - 1 clk i/o (clk i/o /8) tcntn (ctc) ocrnx ocfnx clk tn top bottom top bottom + 1 attiny1634 [preliminary datasheet] 9296c?avr?07/14 82 12.9 register description 12.9.1 tccr0a ? timer/counter control register a bits 7:6 ? com0a[1:0]: compare match output a mode these bits control the output compare pin (oc0a) behavior. if o ne or both of the com0a[1:0] bi ts are set, the oc0a output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of t he com0a[1:0] bits depends on the wgm0[2:0] bit setting. table 12-2 shows the com0a[1:0] bit functionality when the wgm0 [2:0] bits are set to normal or ctc mode (non-pwm). table 12-3 shows com0a[1:0] bit functionality when wg m0[1:0] bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom (see section 12.7.3 ?fast pwm mode? on page 78 ). table 12-4 shows com0a[1:0] bit functionality when wgm0[2 :0] bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top (see section 12.7.4 ?phase correct pwm mode? on page 79 ). bit 7 6 5 4 3 2 1 0 0x1b (0x3b) com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 12-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 12-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected 0 1 wgm02 = 0: normal port operation, oc0a disconnected wgm02 = 1: toggle oc0a on compare match 1 0 clear oc0a on compare match set oc0a at bottom (non-inverting mode) 1 1 set oc0a on compare match clear oc0a at bottom (inverting mode) table 12-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected 0 1 wgm02 = 0: normal port operation, oc0a disconnected wgm02 = 1: toggle oc0a on compare match 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. 83 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bits 5:4 ? com0b[1:0]: compare match output b mode these bits control the output compare pin (oc0b) behavior. if o ne or both of the com0b[1:0] bi ts are set, the oc0b output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of t he com0b[1:0] bits depends on the wgm0[2:0] bit setting. table 12-5 shows the com0b[1:0] bit functionality when the wgm0 [2:0] bits are set to normal or ctc mode (non-pwm). table 12-6 shows com0b[1:0] bit functionality when wg m0[2:0] bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom (see section 12.7.3 ?fast pwm mode? on page 78 ). table 12-7 shows the com0b[1:0] bit functionality when the wgm0[2:0] bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at top (see section 12.7.4 ?phase correct pwm mode? on page 79 ). bits 3:2 ? res: reserved bits these bits are reserved and always read as ?0?. table 12-5. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 12-6. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected 0 1 reserved 1 0 clear oc0b on compare match, set oc0b at bottom (non-inverting mode) 1 1 set oc0b on compare match, clear oc0b at bottom (inverting mode) table 12-7. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected 0 1 reserved 1 0 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 1 1 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. attiny1634 [preliminary datasheet] 9296c?avr?07/14 84 bits 1:0 ? wgm0[1:0]: w aveform generation mode combined with the wgm02 bit found in the t ccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used (see table 12-8 ). operating modes supported by the timer/counter un it are normal mode (counter), clear time r on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section 12.7 ?operating modes? on page 76 ). note: 1. max = 0xff bottom = 0x00 12.9.2 tccr0b ? timer/count er control register b bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, to ensure compatibility with future devices, this bit must be set to ?0? when tccr0b is written while operating in pwm mode. when writing a logic one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a[1:0] bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a[1:0] bits that determines the effe ct of the forced compare. a foc0a strobe does not generate any interrupt nor does it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as ?0?. bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, to ensure compatibility with future devices, this bi t must be set to ?0? when tccr0b is written when operating in pwm mode. when writing a logic one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b[1:0] bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b[1:0] bits that determines the ef fect of the forced compare. a foc0b strobe does not generate any interrupt, nor does it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as ?0?. bits 5:4 ? res: reserved bits these bits are reserved bits in the atmel ? attiny1634 and always read as ?0?. table 12-8. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/counter operating mode top update of ocrx at tov flag set on (1) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4 1 0 0 reserved ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top bit 7 6 5 4 3 2 1 0 0x1a (0x3a) foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 85 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 3 ? wgm02: wavef orm generation mode see description in section 12.9.1 ?tccr0a ? timer/counter control register a? on page 82 . bits 2:0 ? cs0[2:0]: clock select the three clock se lect bits select the clock source to be used by the timer/counter. if external pin modes are used for timer/co unter0, transitions on the t0 pin clock t he counter even if the pin is configured as an output. this feature allows software to control counting. 12.9.3 tcnt0 ? timer/counter register the timer/counter register gives direct a ccess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (re moves) the compare match on the followin g timer clock. modifying the counter (tcnt0) while the counter is running poses the risk of missi ng a compare match between tcnt0 and the ocr0x registers. 12.9.4 ocr0a ? output compare register a the output compare register a contains an 8-bit value that is continuou sly compared with the counter value (tcnt0). a match can be used to generate an output compare inte rrupt or generate a wavefo rm output on the oc0a pin. 12.9.5 ocr0b ? output compare register b the output compare register b contains an 8-bit value that is continuou sly compared with the counter value (tcnt0). a match can be used to generate an output compare inte rrupt or generate a wavefo rm output on the oc0b pin. table 12-9. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 0 0 1 clk i/o /(no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin, clock on falling edge 1 1 1 external clock source on t0 pin, clock on rising edge bit 76543210 0x19 (0x39) tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x18 (0x38) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x17 (0x37) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 86 12.9.6 timsk ? timer/counter interrupt mask register bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to ?1? and the i bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/co unter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register (tifr). bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to ?1? and th e i bit in the status regist er is set, the timer/counter 0 overflow interrupt is enab led. the corresponding interrupt is executed if an overflow in ti mer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter0 interrupt flag register (tifr). bit 0 ? ocie0a: timer/counter0 outp ut compare match a interrupt enable when the ocie0a bit is written to ?1? and the i bit in the stat us register is set, the timer/ counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a comp are match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter0 interrupt flag register (tifr). 12.9.7 tifr ? timer/counter0 interrupt flag register bit 2 ? ocf0b: output compare flag 0 b the ocf0b bit is set when a compare match occurs between the timer/counter and the dat a in ocr0b (output compare register0 b). ocf0b is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. bit 1 ? tov0: timer/co unter0 overflow flag the tov0 bit is set when an overflow occurs in timer/co unter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, tov0 is cleared by writing a logic one to the flag. when the sreg i bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/c ounter0 overflow interrupt is executed. the setting of this flag depends on the wgm0[2:0] bit setting (see table 12-8 on page 84 and section 12-8 ?waveform generation mode bit description? on page 84 ). bit 0 ? ocf0a: output compare flag 0 a the ocf0a bit is set when a compare match occurs between th e timer/counter0 and the data in ocr0a (output compare register0). ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to t he flag. when the i bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. bit 76543 210 0x3a (0x5a) toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a timsk read/write r/w r/w r/w r r/w r/w r/w r/w initial value00000 000 bit 76543210 0x39 (0x59) tov1 ocf1b ocf1a ? icf1 ocf0b tov0 ocf0a tifr read/write r/w r/w r/w r r/w r/w r/w r/w initial value00000000 87 attiny1634 [preliminary datasheet] 9296c?avr?07/14 13. 16-bit timer/counter1 13.1 features true 16-bit design (i.e., allows 16-bit pwm) two independent output compare units double-buffered output compare registers one input capture unit input capture noise canceler clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) variable pwm period frequency generator external event counter four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 13.2 overview the 16-bit timer/counter unit allows a ccurate program execution timing (event management), wave generation, and signal timing measurement. a simplified block diagram of the 16-bit timer/counter is shown in figure 13-1 on page 88 . for the specific placement of i/o pins, see section 1-1 ?pinout of atmel attiny1634? on page 3 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device- specific i/o register and bit locations are listed in section 13.11 ?register description? on page 106 . attiny1634 [preliminary datasheet] 9296c?avr?07/14 88 figure 13-1. 16-bit timer/counter block diagram most register and bit references in this section are writte n in general form. a lowercase ?n? replaces the timer/counter number, and a lowercase ?x? replaces the output compare unit ch annel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing ti mer/counter1 counter value, etc. 13.2.1 registers the timer/counter (tcnt1), output compare re gisters (ocr1a/b), and input capture regi ster (icr1) are all 16-bit registers. special procedures must be followed when accessing the 16 -bit registers. these proc edures are described in section 13.10 ?accessing 16-bit registers? on page 103 . the timer/counter control registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated as ?int.req.? in the figure ) signals are all visible in the timer inte rrupt flag register (tifr). all interrupts are individually masked wi th the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t1 pin. th e clock select logic block controls which clock source and edge the timer/ counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t1 ). control logic tcntn timer/counter count clear direction clk tn ocrna ocrnb icrn tccrna tccrnb = edge detector (from prescaler) clock select top bottom tovn (int. req.) ocna (int. req.) tn waveform generation fixed top value data bus = = = 0 ocna ocnb (int. req.) waveform generation noise canceler ocnb (from analog comparator output) icfn (int. req.) edge detector icpn 89 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the double-buffered output compare regi sters (ocr1a/b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable fr equency output on the output compare pin (oc1a/b) (see section 13.6 ?output compare units? on page 92 ). the compare match event also sets the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. the input capture register can capture the timer/counter value at a given external (edge-triggered) event on either the input capture pin (icp1) or on the analog comparator pins (see section 19. ?analog comparator? on page 169 ). the input capture unit includes a digital filtering unit (noise cancele r) for reducing the chance of capturing noise spikes. in some operating modes the top value, or maximum timer/counter value, can be defined by either the ocr1a register, the icr1 register, or by a set of fixed values. when usin g ocr1a as top value in a pwm mode, the ocr1a register cannot be used for generating a pwm output. however, in th is case the top value is double-buffered, allowing the top value to be changed during run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as a pwm output. 13.2.2 definitions the following definitions are used extensively throughout the section. 13.2.3 compatibility the 16-bit timer/counter has been updated and impr oved from previous versions of 16-bit avr ? timer/counter. this 16-bit timer/counter is fully compatible with the earlier version regarding: all i/o register address locations related to the 16-bi t timer/counter, including timer interrupt registers bit locations inside all 16-bit timer/counter r egisters, including timer interrupt registers interrupt vectors the following control bits have been renamed but retai ned the same functionality and register locations: pwm10 is changed to wgm10 pwm11 is changed to wgm11 ctc1 is changed to wgm12 the following bits have been added to the 16-bit timer/counter control registers: 1a and 1b are added to tccr1a wgm13 is added to tccr1b the 16-bit timer/counter has improvements that affect reverse compatibility in so me special cases. 13.3 timer/counter clock sources the timer/counter can be clocked by an internal or an extern al clock source. the clock sour ce is selected by the clock select logic which is controlled by the clo ck select (cs1[2:0]) bits located in the timer/counter control register b (tccr1b). for details on clock sources and prescaler, see section 14. ?timer/counter prescaler? on page 112 . table 13-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equa l to the highest value in the count sequence. the top value can be assigned a fixed value or the value stored in a register. the assignment depends on the operating mode (see table 13-5 on page 107 ). attiny1634 [preliminary datasheet] 9296c?avr?07/14 90 13.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bidrectional counter unit. figure 13-2 shows a block diagram of the counter and its surroundings. figure 13-2. counter unit block diagram description of internal signals used in figure 13-2 : count increment or decrement tcnt1 by 1 direction select between increment and decrement clear clear tcnt1 (set all bits to ?0?) clk t1 timer/counter clock top indicates that tcnt1 has reached maximum value bottom indicates that tcnt1 has reached minimum value (?0?) the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) containing the upper eight bits of the counter, and counter low (tcnt1l) contai ning the lower eight bits. the tcnt1h register can only be indirectly accessed by the cpu. when the cpu does an access to the tcnt1h i/o location, the cpu accesses the high-byte temporary register (temp). the temporary register is updat ed with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register value when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that produces unpredictable results. the spec ial cases are described in the sections where they are of importance. depending on the operating mode used, the counter is cleared, incremented, or decrement ed at each timer clock (clk t1 ). the clk t1 can be generated from an external or internal clock sour ce, selected by th e clock select bits (cs1[2:0]). when no clock source is selected (cs1[2:0] = 0), the timer is stopp ed. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t1 is present or not. a cpu write overrides (has prio rity over) all counter cl ear or count operations. the counting sequence is determined by the setting of th e waveform generation mode bits (wgm1[3:0]) located in the timer/counter control regist ers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms ar e generated on the output compare out puts oc1x. for more details about advanced counting sequences and waveform generation, see section 13.8 ?operating modes? on page 95 . the timer/counter overflow flag (tov1) is set according to the operating mode selected by the wgm1[3:0] bits. tov1 can be used for generating a cpu interrupt. bottom top tovn (int. req.) data bus (8-bit) control logic tcntnh (8-bit) tcntn (16-bit counter) tcntnl (8-bit) temp (8-bit) clk tn clear count direction edge detector (from prescaler) clock select tn 91 attiny1634 [preliminary datasheet] 9296c?avr?07/14 13.5 input capture unit the timer/counter incorporates an input capture unit that can ca pture external events and give them a timestamp indicating time of occurrence. the external signal in dicating an event, or multiple events, can be applied via the icp1 pin or instead via the analog-comparator unit. the timestamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. alternatively, the timestamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 13-3 on page 91 . the elements of the block diagram that are not directly a part of t he input capture unit are gray shaded. the lowercase ?n? in register and bit names indicates the timer/counter number. figure 13-3. input capture unit block diagram when a change of the logic level (an event) occurs on the in put capture pin (icp1) or on the analog comparator output (aco) and this change corresponds to the setting of the edge de tector, a capture is triggered. when a capture is triggered, the 16-bit value of the counter (tcnt1) is wr itten to the input capture r egister (icr1). the input capture flag (icf1) is set a t the same system clock as the t cnt1 value is copied to the icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. alternatively, the icf1 flag can be cleared via software by writing a logic one to its i/o bit location. reading the 16-bit value in the input capt ure register (icr1) is done by first read ing the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is c opied to the high-byte temporary register (temp). when the cpu reads the icr1h i/o location, it accesses the temp register. the icr1 register can only be written when using a waveform gener ation mode that utilizes the ic r1 register for defining the counter?s top value. in these cases, t he waveform generation mode (wgm1[3:0]) bits must be set before the top value can be written to the icr1 register. when wr iting the icr1 register, the high byte mu st be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16 -bit registers, see section 13.10 ?accessing 16-bit registers? on page 103 . icfn (int. req.) icrnl (8-bit) icrnh (8-bit) icrn (16-bit register) temp (8-bit) tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) noise canceler analog comparator edge detector icncn acic* aco* write + - icesn icpn attiny1634 [preliminary datasheet] 9296c?avr?07/14 92 13.5.1 input capture trigger source the main trigger source for the input capture unit is the in put capture pin (icp1). timer/co unter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsra). be aware that changing the trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and t he analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin ( figure 14-2 on page 113 ). the edge detector is also identical. howe ver, when the noise canceler is enabled, additional logic is inserted before the edge detector, which in creases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in waveform generation mode that uses icr1 to define top. an input capture can be triggered by softw are by controlling the port of the icp1 pin. 13.5.2 noise canceler the noise canceler uses a simple digital filtering technique to improve noise immunity. consecutive samples are monitored in a pipeline four units deep. the signal going to the edge det ector is allowed to change only when all four samples are equal. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in time r/counter control register b (tccr1b). when enabled , the noise canceler intr oduces an additiona l delay of four system cloc k cycles to a change applied to the input and before icr1 is updated. the noise canceler uses the system clock directly and is therefore not affected by the prescaler. 13.5.3 using the input capture unit when using the input capture unit, the main challenge is to assign enough processor capacity for handling the incoming events. the time between two events is cr itical. if the processor has not read the ca ptured value in the icr1 register before the next event occurs, the icr1 is overwrit ten with a new value. in this case, the result of the capture will be incorrect. when using the input capture interrupt, the icr1 register should be read in the interrupt handler routine as early as possible. even though the input capture interrupt has relatively high pr iority, the maximum interrupt response time depends on the maximum number of clock cycles it takes to handle any of the other interrupt requests. it is not advisable to use the input capture unit in any operat ing mode when the top value (resolution) is actively changed during operation. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after the edge is changed, the input capture flag (icf1) must be cleared by software (writing a lo gic one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 13.6 output compare units the 16-bit comparator continuously comp ares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x, the comparator signals a match. a match sets the output compare flag (ocf1x) at the next time r clock cycle. if enabled (ocie1x = 1), the output compare flag gen erates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternativel y, the ocf1x flag can be cleared via softwa re by writing a logic one to its i/o bit location. the waveform generator uses the match signal to g enerate an output according to the operating mode set by the waveform generation mode (wgm1[3:0]) bits and compare out put mode (com1x[1:0]) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some operating modes ( section 13.8 ?operating modes? on page 95 ). a special feature of output compare unit a allows to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 13-4 on page 93 shows a block diagram of the output compare unit . the lowercase ?n? in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the ?x ? indicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compar e unit are gray shaded. 93 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 13-4. output comp are unit, block diagram the ocr1x register is double-buffered when using any of the twelve pulse width modulation (pwm) modes. double- buffering is disabled for the normal and clear timer on co mpare (ctc) operating modes. double-buffering synchronizes the update of the ocr1x compare register to either top or bottom of the counti ng sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thus making the output glitch-free. the ocr1x register access may seem complex, but this is no t the case. when the double-buffering is enabled, the cpu has access to the ocr1x buffer register and if double-buffering is disabled, the cpu accesses the ocr1x directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/ counter does not update this register automatically as the tcnt1 and i cr1 register). therefore ocr1x is not r ead via the high-byte temporary register (temp). however, it is a good practice to read the low byte fi rst as is done when accessing other 16-bit registers. writing the ocr1x registers must be done via the temp register because the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. when the high-byte i/o location is written by the cpu, the te mp register is updated by the value written. then, when the low byte (ocr1xl) is written to t he lower eight bits, the high byte is copied to the upper eight bits of either the ocr1x buffer or ocr1x co mpare register in the same system clock cycle. for more information on how to access the 16 -bit registers, see section 13.10 ?accessing 16-bit registers? on page 103 . 13.6.1 force output compare in non-pwm waveform generation modes the match output of the comparator can be forced by writing a ?1? to the force output compare (1x) bit. forcing compare ma tch does not set the ocf1x flag or reload /clear the timer, but the oc1x pin is updated as if a real compare match had occurr ed (the com1x[1:0] bits se ttings define whether the oc 1x pin is set, cleared, or toggled). 13.6.2 compare match blocking by tcnt1 write all cpu writes to the tcnt1 register block any compare match that occurs in the next timer clock cycle even when the timer is stopped. this feature allows ocr1x to be initialized to the same value as t cnt1 without triggering an interrupt when the timer/counter clock is enabled. ocrnxl buf. (8-bit) ocrnxh buf. (8-bit) ocrnx buffer (16-bit register) temp (8-bit) ocrnxl (8-bit) ocfnx (int. req.) ocrnxh (8-bit) ocrnx (16-bit register) = (16-bitcomparator) wgmn3:0 comnx1:0 waveform generator tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) ocnx top bottom attiny1634 [preliminary datasheet] 9296c?avr?07/14 94 13.6.3 using the ou tput compare unit because writing tcnt1 in any operating mode blocks all compare matches for one timer clock cycle, risks arise from changing tcnt1 while using any of the output compare channels, regardless of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare match is missed, resulting in incorrect waveform generation. do not write the tcnt1 equal to top in pwm m odes with variable top values. the compare match for the top is ignored and the counter continues to 0xffff. similarly, do not writ e the tcnt1 value equal to bottom when the counter is down-counting. the setup of the oc1x should be performed bef ore setting the data direction register for the port pin to output. the easiest way to set the oc1x value is to use the force output compare (1x) str obe bits in normal mode. the oc1x register retains its value even when changing between waveform generation modes. be aware that the com1x[1:0] bits are not double-buffered toge ther with the compare value. changing the com1x[1:0] bits takes effect immediately. 13.7 compare match output unit the compare output mode (com1x[1:0]) bi ts have two functions. the waveform ge nerator uses the com1x[1:0] bits for defining the output compare (oc1x) state at the next compare match. secondly , the com1x[1:0] bits control the oc1x pin output source. figure 13-5 on page 94 shows a simplified schematic of the logic af fected by the com1x[1: 0] bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the ge neral i/o port control registers (ddr and port) affected by the com1x[1:0] bits are displayed. when referring to the oc1x state, the reference is for the internal oc1x register, not the oc1x pin. if a system reset occurs, t he oc1x register is reset to ?0?. figure 13-5. compare match output unit, schematic (non-pwm mode) the general i/o port function is overridden by the output co mpare (oc1x) from the waveform generator if either of the com1x[1:0] bits are set. however, the oc 1x pin direction (input or output) is st ill controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc1x pin (ddr_oc1x) must be set as the output before the oc1x value is visible on the pin. the port override functi on is generally independent of t he waveform generation mode, but there are some exceptions. see table 13-2 on page 106 , table 13-3 on page 106 and table 13-4 on page 107 for more information. the design of the output compare pin logic allows initialization of the oc1x state before the output is enabled. note that some com1x[1:0] bit settings are reserv ed for certain operating modes (see section 13.11 ?register description? on page 106 ). the com1x[1:0] bits have no ef fect on the input capture unit. data bus 0 1 q d comnx1 comnx0 focnx ocnx waveform generator q d port q d ddr ocnx pin clk i/o 95 attiny1634 [preliminary datasheet] 9296c?avr?07/14 13.7.1 compare output mode and waveform generation the waveform generator uses the com1x[1:0] bits differently in normal, ctc, and pwm modes. for all modes, setting the com1x[1:0] = 0 tells the waveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-pwm modes, see table 13-2 on page 106 . for fast pwm mode, see table 13- 3 on page 106 and for phase correct and phase and frequency correct pwm, see table 13-4 on page 107 . a change in the com1x[1:0] bits state ha s an effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the 1x strobe bits. 13.8 operating modes the operating mode, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm1[3:0]) and compare output mode (com1x[1:0]) bits. the compare output mode bits do not affect the counting sequence while the waveform generati on mode bits do. the com1x[1:0] bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes, the com1x[1:0] bits control whether the output should be se t, cleared, or toggle at a compare match (see section 13.7 ?compare match output unit? on page 94 ). for detailed timing information, see section 13.9 ?timer/counter timing diagrams? on page 101 . 13.8.1 normal mode the simplest operating mode is the normal mode (wgm1[3:0] = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counte r simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) is set in the same timer clock cycle when the tcnt1 becomes ?0?. the tov1 flag in this case behaves as a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in normal mode; a new counter value can be written at any time. the input capture unit is easy to use in normal mode. howeve r, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to exte nd the resolution for the capture unit. the output compare units can be used to generate interrupts at a given time . using the output compare to generate waveforms in normal mode is not recommended because this occupies too much cpu time. 13.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm1[3:0] = 4 or 12) the ocr1a or icr1 register is used to manipulate the counter resolution. in ctc mode the counter is cleared to ?0? when the count er value (tcnt1) matches either the ocr1a (wgm1[3:0] = 4) or the icr1 (wgm1[3:0] = 12). the ocr1a or icr1 define the top value for the counter and therefore its resolution as well. this mode allows gr eater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 13-6 on page 95 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 13-6. ctc mode, timing diagram 12 tcntn (comna[1:0] = 1) ocna (toggle) period 3 ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 4 attiny1634 [preliminary datasheet] 9296c?avr?07/14 96 an interrupt can be generated each time the counter value reac hes the top value by either us ing the ocf1a or icf1 flag according to the register used to define the top value. if th e interrupt is enabled, the inte rrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with no prescaler value or a low prescaler value must be done with care because the ctc mode does not have the double-buffering feature. if the new value written to ocr1 a or icr1 is lower than the current value of tcnt1, the counter misses the compare match. the counter then has to count to its maximu m value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases, this feature is not desirable. an alternative is to use the fast pwm mode using ocr1a for defining top (wgm1[3:0] = 15) be cause the ocr1a is then double-buffered. for generating a waveform output in ctc mo de, the oc1a output can be set to toggle its logic level on each compare match by setting the compare output mode bits to toggle mode (com1a[1:0] = 1). the oc1a value is not visible on the port pin unless the data direction for the pin is set to output (ddr_ oc1a = 1). the waveform generated has a maximum frequency of 1a = f clk_i/o /2 when ocr1a is set to ?0? (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler fa ctor (1, 8, 64, 256, or 1024). as for normal operating mode, the tov1 flag is set in the same timer clock cycle in which t he counter counts from max to 0x0000. 13.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm1[3: 0] = 5, 6, 7, 14, or 15) provides a high-frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top, then restarts from bottom. in non-inverti ng compare output mode the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x, and set at bottom. in inverting compare output mode the output is set on compare matc h and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be two times higher than the phase correct and phase and frequency correct pwm modes that use dual-slope operation. a high frequency makes the fast pwm mode highly suitable for power regulation, rectification, and dac applications and also allows external components (coils, capacitors) of small physical size, thus reducing overall system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the count er value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm1[3:0] = 5, 6, or 7), the value in icr1 (wgm1[3:0] = 14), or the value in ocr1a (wgm1[3:0] = 15). the counter is then cleared at the following timer clock cycl e. the timing diagram for the fast pwm mode can be seen in figure 13-7 . the figure shows fast pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is displayed in the timing diagram as a histogram for illustrating the si ngle-slope operation. the diagram includes non-inverted and inverted pwm outputs. the sm all horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag is set when a compare match occurs. f ocna f clk_i/o 2n 1 ocrna + () ----------------------------------------------------- = r fpwm log top 1 + () log 2 () --------------------------------- = 97 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 13-7. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the c ounter reaches top. in addition, the oc1a or icf1 flag is set at the same timer clock cycle as tov1 is set when either ocr1a or icr1 is used for defining the to p value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. when changing the top value, the program mu st ensure that the new top value is hi gher than or equal to the value of all the compare registers. if the top valu e is lower than any of the compare regi sters, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unused bits are masked to ?0? when any of the ocr1x registers are written. the procedure for updating icr1 differs from updating ocr1a wh en used for defining the top value. the icr1 register is not double-buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value writt en is lower than the current value of tcnt1. the result is then that the counter misses the compare match at the top value. and so the counter has to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double-buffered. this feature allows the ocr1a i/o location to be written anytime. w hen the ocr1a i/o location is written, the value written is placed in the ocr1a buffer register. the ocr1a compare regi ster is then updated with the value in the buffer register at the next timer clock cycle the tcnt1 matc hes top. the update is done at the same timer cl ock cycle as the tcnt1 is cleared and the tov1 flag is set. using the icr1 register for defining top works well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. ho wever, if the base pwm frequency is actively changed (by changing the top value), using the ocr1a as top is clear ly a better choice due to its double-buffer feature. in fast pwm mode the compare units allow generation of pwm wa veforms on the oc1x pins. sett ing the com1x[1:0] bits to ?2? produces a non-inverted pwm and an inverted pwm output can be generated by setting the com1x[1:0] to ?3? (see table 13-3 on page 106 ). the actual oc1x value is only visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1. the counter is cleared (changes from top to bottom ) by clearing (or setting) the oc1x register at the timer clock cycle. the pwm frequency for the output can be calculated with this equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1x is set equal to bottom (0x0000), th e output is a narrow spike for each top+1 timer clock cycle. setting the ocr1x equal to top results in a constant high or low output (depending on the polarity of the output set by the com1x[1:0] bits.) 12345 tcntn (comnx[1:0] = 2) ocnx ocnx period ocrnx/ top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 67 8 (comnx[1:0] = 3) f ocnxpwm f clk_i/o n1top + () ----------------------------------- - = attiny1634 [preliminary datasheet] 9296c?avr?07/14 98 a frequency (with 50% duty cycle) waveform output in fast pw m mode can be achieved by setting oc1a to toggle its logic level on each compare match (com1a[1:0] = 1). t he waveform generated has a maximum frequency of 1a = f clk_i/o /2 when ocr1a is set to ?0? (0x0000). this feature is similar to the oc1a toggle in ctc mode except the double-buffer feature of the output compare unit is enabled in the fast pwm mode. 13.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pw m mode (wgm1[3:0] = 1, 2, 3, 10, or 11) provides a high- resolution phase correct pwm waveform generation option. t he phase correct pwm mode is, the same way as the phase and frequency correct pwm mode, based on a dual-slope o peration. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inve rting compare output mode th e output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x wh ile up-counting and set on the compare match while down- counting. in inverting output compare mode the operation is inverted . the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until th e counter value matches any one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm1[3:0] = 1, 2, or 3), the value in icr1 (wgm1[3:0] = 10), or the value in ocr1a (wgm1[3:0] = 11). the counter has then reached the top and changes the count direction. the tcnt1 value is equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode can be seen in figure 13-8 on page 98 . the figure shows phase correct pwm mode when ocr1a or i cr1 is used to define top. the tcnt1 value is displayed in the timing diagram as a histogram to illustrate the dual-sl ope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represen t compare matches between ocr1x and tcnt1. the oc1x interrupt flag is set when a compare match occurs. figure 13-8. phase correct pwm mode, timing diagram r pcpwm log top 1 + () log 2 () --------------------------------- = 1 2 34 tcntn (comnx[1:0] = 2) (comnx[1:0] = 3) ocnx ocnx period tovn interrupt flag set (interrupt on bottom) ocrnx/ top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 99 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the timer/counter overflow flag (tov1) is set each time th e counter reaches bottom. when either ocr1a or icr1 is used for defining the top va lue, the oc1a or icf1 flag is set accord ingly at the same timer clock cycle as the ocr1x registers are updated with the double-buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value, the program must ensure that the new top value is gr eater than or equal to the value of all the compare registers. if the top value is lower than any of the compare registers, a compar e match never occurs between the tcnt1 and the ocr1x. note that when using fixed top values, the unused bits are masked to ?0? when any of the ocr1x registers are written. as the third period shown in figure 13-8 on page 98 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can resu lt in an unsymmetrical output. this is due to the time of update of the ocr1x register. because the ocr1x update occurs at top, the pwm period st arts and ends at top. this implies that the length of the falling slope is determined by t he previous top value while the length of the rising slope is determined by the new top value. when these two values differ, the two slopes of the period differ in length. the difference in length causes the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value, there ar e practically no differences between the two operating modes. in phase correct pwm mode the compare units allow genera tion of pwm waveforms on the oc1x pins. setting the com1x[1:0] bits to ?2? produces a non-inverted pwm and an inverted pwm output can be generated by setting the com1x[1:0] to ?3? (see table 13-4 on page 107 ). the actual oc1x value is only visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing ) the oc1x register at the compare match between ocr1x and tcnt1 when the counter incr ements and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated with this equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x regist er represent special cases when generatin g a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom, the ou tput is continuously low and if the ocr1x is set equal to top, the output is continuously high for non-inverted pwm mode. for inverted pwm, the output has the opposite logic values. 13.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation or phas e and frequency correct pwm mode (wgm1[3:0] = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, the same way as the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare matc h between tcnt1 and ocr1x while up-counting and set on the compare match while down-counting. in inverting compare out put mode the operation is invert ed. the dual-slope operation gives a lower maximum operation frequency compared to the si ngle-slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct and the phas e and frequency correct pwm mode is the time the ocr1x register is updated by the oc r1x buffer register (see figure 13-8 on page 98 and figure 13-9 on page 100 ). the pwm resolution for the phase and frequency correct pw m mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x 0003) and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated using the following equation: f ocnxpcpwm f clk_i/o 2n top ------------------------------ - = r pfcpwm log top 1 + () log 2 () --------------------------------- = attiny1634 [preliminary datasheet] 9296c?avr?07/14 100 in phase and frequency correct pwm mode the counter is incr emented until the counter value matches either the value in icr1 (wgm1[3:0] = 8) or the value in ocr1a (wgm1[3:0] = 9). the counter has then reached the top and changes the count direction. the tcnt1 value will be equal to top for o ne timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode can be seen in figure 13-9 on page 100 . the figure shows phase and frequency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is displayed in the timing diagram as a histogram for illustrating the dual-slope o peration. the diagram includes non-inve rted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compar e matches between ocr1x and tcnt1. the oc1x interrupt flag is set when a compare match occurs. figure 13-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow fl ag (tov1) is set at the same timer clock cycl e as the ocr1x regist ers are updat ed with the double-buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value, the program must ensure that the new top value is higher or equal to the value of all the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. as shown in figure 13-9 on page 100 , the output generated is, in contrast to the phase correct mode, symmetrical in all periods. because the ocr1x registers are updated at bottom, the length of the rising and the falling slopes is always equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top works well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. ho wever, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is cl early a better choice due to its double-buffer feature. in phase and frequency correct pwm mode the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x[1:0] bits to ?2? produces a non-inverted pw m and an inverted pwm output can be generated by setting the com1x[1:0] to ?3? (see table 13-4 on page 107 ). the actual oc1x value is only visi ble on the port pin if the data direction for the port pin is set as output (ddr_oc 1x). the pwm waveform is gen erated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter in crements and clearing (or sett ing) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be calculated with this equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). 1 2 34 tcntn (comnx[1:0] = 2) (comnx[1:0] = 3) ocnx ocnx period ocna interrupt flag set or icfn interrupt flag set (interrupt on top) ocrnx/ top update and tovn interrupt flag set (interrupt on bottom) f ocnxpfcpwm f clk_i/o 2n top ------------------------------ - = 101 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the extreme values for the ocr1x regist er represent special cases when generatin g a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equa l to bottom, the output is c ontinuously low and if set equal to top, the output is set to high for non-inverted pwm mode. for inve rted pwm, the output has the opposite logic values. 13.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interr upt flags are set and when th e ocr1x register is updated with the ocr1x buffer value (only for modes utilizing double-buffering). figure 13-10 shows a timing diagram for the setting of ocf1x. figure 13-10.timer/counter timing diagram, setting of ocf1x, no prescaling figure 13-11 shows the same timing data but with the prescaler enabled. figure 13-11.timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) ocrnx - 1 clk i/o (clk i/o /1) tcntn ocrnx ocfnx clk tn ocrnx ocrnx value ocrnx + 1 ocrnx + 2 ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2 attiny1634 [preliminary datasheet] 9296c?avr?07/14 102 figure 13-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode, the ocr1x register is updated at bottom. the timing diagrams are the same, but top should be replaced by bottom, top-1 by bottom+1, etc. the same renaming ap plies for modes that set the tov1 flag at bottom. figure 13-12.timer/counter ti ming diagram, no prescaling figure 13-13 on page 102 shows the same timing data but with the prescaler enabled. figure 13-13.timer/counter timi ng diagram, with prescaler (f clk_i/o /8) top - 1 clk i/o (clk i/o /1) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn top old ocrnx value new ocrnx value bottom bottom + 1 top - 1 top top -1 top -2 top - 1 top bottom bottom + 1 top - 1 top top - 1 top - 2 clk i/o (clk i/o /8) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn old ocrnx value new ocrnx value 103 attiny1634 [preliminary datasheet] 9296c?avr?07/14 13.10 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr ? cpu via the 8-bit data bus. the 16- bit register must be byte-accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporarily storing the high byte of the 16-bit access. the same temporary regist er is shared by all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register and the low byte written are both copied to the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit regist er is copied to the temporary register in the same clock cycle as the low byte is read. not all 16-bit accesses use the temporary register for the high byte. reading the ocr1a/b 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before th e high byte. the following code examples show how to access the 16-bit timer registers, assuming that no interrupts update the temporary register. the same principle can be used for accessi ng the ocr1a/b and icr1 regist ers. note that when using ?c?, the compiler handles the 16-bit access. note: see section 4.2 ?code examples? on page 7 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the in terrupt is corrupted. therefore, when both the main code and the interrupt code update the temporary regist er, the main code must disable the interrupts during the 16- bit access. assembly code examples ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code examples unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... attiny1634 [preliminary datasheet] 9296c?avr?07/14 104 the following code examples show how to do an atomic read of the tcnt1 register conten ts. reading any of the ocr1a/b or icr1 registers can be done based on the same principle. note: see section 4.2 ?code examples? on page 7 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 105 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the following code examples show how to do an atomic writ e of the tcnt1 register conten ts. writing any of the ocr1a/b or icr1 registers can be done based on the same principle. note: see section 4.2 ?code examples? on page 7 . the assembly code example requires the r17:r16 register pair to contain the value to be written to tcnt1. 13.10.1 reusing the temporary high-byte register if writing to more than one 16-bit regist er where the high byte is the same for a ll registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described pr eviously also applies in this case. assembly code example tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } attiny1634 [preliminary datasheet] 9296c?avr?07/14 106 13.11 register description 13.11.1 tccr1a ? timer/counter1 control register a bits 7:6 ? com1a[1:0]: compar e output mode for channel a bits 5:4 ? com1b[1:0]: compar e output mode for channel b the com1a[1:0] and com1b[1:0] co ntrol the behavior of the output compare pins (oc1a and oc1b respectively). if one or both of the com1a[1:0] bits are written to ?1?, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the com1b[ 1:0] bit are written to ?1?, the oc1b ou tput overrides the normal port functionality of the i/o pin it is connected to. however, note that, to enab le the output driver, the data direction register (ddr) bit corresponding to the oc1a or oc1b pin must be set. when the oc1a or oc1b is connected to the pin, the func tion of the com1x[1:0] bits depends on the wgm1[3:0] bits setting. table 13-2 shows com1x[1:0] bit functional ity when wgm1[3:0] bits are set to normal or ctc mode (non-pwm). table 13-3 shows com1x[1:0] bit functionality when wg m1[3:0] bits are set to fast pwm mode. note: 1. a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. in this case, the com- pare match is ignored but the set or clear is done at bottom (see section 13.8.3 ?fast pwm mode? on page 96 ). bit 76543210 (0x72) com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-2. compare output mode, non-pwm com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 0 1 toggle oc1a/oc1b on compare match 1 0 clear oc1a/oc1b on compare match (set output to low level) 1 1 set oc1a/oc1b on compare match (set output to high level) table 13-3. compare output mode, fast pwm (1) com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 0 1 wgm13=0: normal port operation, oc1a/oc1b disconnected wgm13=1: toggle oc1a on compare match, oc1b reserved 1 0 clear oc1a/oc1b on compare match, set oc1a/oc1b at bottom (non- inverting mode) 1 1 set oc1a/oc1b on compare match, clear oc1a/oc1b at bottom (inverting mode) 107 attiny1634 [preliminary datasheet] 9296c?avr?07/14 table 13-4 shows com1x[1:0] bit functionality when wgm1[3:0] bits are set to phase correct or phase and frequency correct pwm mode. note: 1. a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set (see section 13.8.4 ?phase correct pwm mode? on page 98 ). bits 1:0 ? wgm1[1:0]: w aveform generation mode these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation is to be used (see table 13-5 on page 107 ). operating modes s upported by the timer/counter unit are normal mode (counter), clear timer on compare match (ctc ) mode, and three types of pulse width modulation (pwm) modes. ( section 13.8 ?operating modes? on page 95 ). table 13-4. compare output mode, phase correct and phase and frequency correct pwm (1) com1a1 com1b1 com1a0 com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected 0 1 wgm13=0: normal port operation, oc1a/oc1b disconnected wgm13=1: toggle oc1a on compare match, oc1b reserved 1 0 clear oc1a/oc1b on compare match when up-counting set oc1a/oc1b on compare match when down-counting 1 1 set oc1a/oc1b on compare match when up-counting clear oc1a/oc1b on compare match when down-counting table 13-5. waveform generation modes mode wgm1[3:0] operating mode top update of ocr1 x at tov1 flag set on 0 0000 normal 0xffff immediate max 1 0001 pwm, phase correct, 8-bit 0x00ff top bottom 2 0010 pwm, phase correct, 9-bit 0x01ff top bottom 3 0011 pwm, phase correct, 10-bit 0x03ff top bottom 4 0100 ctc ( clear timer on compare ) ocr1a immediate max 5 0101 fast pwm, 8-bit 0x00ff top top 6 0110 fast pwm, 9-bit 0x01ff top top 7 0111 fast pwm, 10-bit 0x03ff top top 8 1000 pwm, phase and freq. correct icr1 bottom bottom 9 1001 pwm, phase and freq. correct ocr1a bottom bottom 10 1010 pwm, phase correct icr1 top bottom 11 1011 pwm, phase correct ocr1a top bottom 12 1100 ctc ( clear timer on compare ) icr1 immediate max 13 1101 reserved ? ? ? 14 1110 fast pwm icr1 top top 15 1111 fast pwm ocr1a top top attiny1634 [preliminary datasheet] 9296c?avr?07/14 108 13.11.2 tccr1b ? timer/counter1 control register b bit 7 ? icnc1: input capture noise canceler setting this bit (to ?1?) activates the input capture noise cancel er. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal-valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) is used to trigger a capture event. when the ices1 bit is written to ?0?, a falling (negative) edge is used as trigger and when t he ices1 bit is written to ?1?, a rising (positive) edge trigger s the capture. when a capture is triggered according to the ices1 setting, the counter value is copied to the input capture register (icr1). the event sets the input capture flag (icf1) and this can be us ed to cause an input capture interrupt if this interrupt is enabled. when the icr1 is used as top value (see the description of the wgm1[3:0] bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and the input capture function thus disabled. bit 5 ? res: reserved bit this bit is a reserved bit in the atmel ? attiny1634 and always reads as ?0?. bits 4:3 ? wgm1[3:2]: w aveform generation mode these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation is to be used (see table 13-5 on page 107 ). operating modes s upported by the timer/counter unit are normal mode (counter), clear timer on compare match (ctc ) mode, and three types of pulse width modulation (pwm) modes (see section 13.8 ?operating modes? on page 95 ). bits 2:0 ? cs1[2:0]: clock select bits the three clock sele ct bits select the clock source to be used by the ti mer/counter (see figure 13-10 and figure 13-11 ). if external pin modes are used for the timer/counter1, trans itions on the t1 pin clock the counter even if the pin is configured as an output. this feature allows the software to control counting. bit 7 6 5 4 3 2 1 0 (0x71) icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-6. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped) 0 0 1 clk i/o /1 (no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin, clock on falling edge 1 1 1 external clock source on t1 pin, clock on rising edge 109 attiny1634 [preliminary datasheet] 9296c?avr?07/14 13.11.3 tccr1c ? timer/counter1 control register c bit 7 ? foc1a: force output compare for channel a bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm1[3:0] bits specify a non-pwm mode . however, to ensure compatibility with future devices, while o perating in pwm mode, these bits must be set to ?0? when tccr1b is written. when writing a logic one to the foc1a/foc1b bit, an immediate compare match is forced on the waveform generation unit. the oc1a/oc1b output is changed according to its com1x[1:0] bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value pr esent in the com1x[1:0] bits that dete rmines the effect of the forced compare. a foc1a/foc1b strobe does not generate any interrupt nor does it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as ?0?. 13.11.4 tcnt1h and tcnt1l ? timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l, combi ned tcnt1) give direct access to the timer/counter unit 16-bit counter for read as well as write operations. to ensure that both high as well as low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high-byte register (temp). this temporary regist er is shared by all the ot her 16-bit registers (see section 13.10 ?accessing 16-bit registers? on page 103 ). modifying the counter (tcnt1) while the counter is running, poses the risk of missing a compare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the follo wing timer clock for all compare units. 13.11.5 ocr1ah and ocr1al ? output compare register 1 a bit 7 6 5 4 3 2 1 0 (0x70) foc1a foc1b ? ? ? ? ? ? tccr1c read/write w w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6f) tcnt1[15:8] tcnt1h (0x6e) tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x6d) ocr1a[15:8] ocr1ah (0x6c) ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 110 13.11.6 ocr1bh and ocr1bl ? output compare register 1 b the output compare registers contain a 16 -bit value that is continuously compar ed with the counter value (tcnt1). a match can be used to generate an output compare interrupt or to generate a waveform output on the oc1x pin. the output compare registers are 16 bits in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performe d using an 8-bit temporary high -byte register (temp). this temporary register is shared by al l the other 16-bit registers (see section 13.10 ?accessing 16-bit registers? on page 103 ). 13.11.7 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/co unter1). the input capture can be used for defining the counter top value. the input capture register is 16 bits in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high -byte register (temp). this temporary register is shared by all th e other 16-bit registers (see section 13.10 ?accessing 16-bit registers? on page 103 ). 13.11.8 timsk ? timer/counter interrupt mask register bit 7 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to ?1? and the i flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see section 10. ?interrupts? on page 47 ) is executed when the tov1 flag located in tifr is set. bit 6 ? ocie1a: timer/counter1, outp ut compare a match interrupt enable when this bit is written to ?1? and the i flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector (see section 10. ?interrupts? on page 47 ) is executed when the ocf1a flag located in tifr is set. bit 5 ? ocie1b: timer/counter1, outp ut compare b match interrupt enable when this bit is written to ?1? and the i flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector (see section 10. ?interrupts? on page 47 ) is executed when the ocf1b flag located in tifr is set. bit 4 ? res: reserved bit this bit is a reserved bit in the atmel ? attiny1634 and always reads as ?0?. bit 76543210 (0x6b) ocr1b[15:8] ocr1bh (0x6a) ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x69) icr1[15:8] icr1h (0x68) icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 7 6 5 4 3 2 1 0 0x3a (0x5a) toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a timsk read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 111 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 3 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to ?1? and the i flag in the status re gister is set (interrupts globally enabled), the timer/counter i nput capture interrupt is enabled. the corresponding interrupt vector (see section 10. ?interrupts? on page 47 ) is executed when the icf1 flag located in tifr is set. 13.11.9 tifr ? timer/counter interrupt flag register bit 7 ? tov1: timer/counter1, overflow flag the setting of this flag depends on the wgm1[3:0] bits setting. in normal and ctc modes the tov1 flag is set when the timer overflows. see table 13-5 on page 107 for the tov1 flag behavior when using another wgm1[3:0] bit setting. tov1 is automatically cleared when the ti mer/counter1 overflow inte rrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 6 ? ocf1b: timer/counter1 , output compare b match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (1b) strobe does not set the ocf1b flag. ocf1b is automatically cleared when the ou tput compare match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. bit 5 ? ocf1a: timer/counter1 , output compare a match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (1a) strobe does not set the ocf1a flag. ocf1a is automatically cleared when the ou tput compare match a interrupt vector is executed. alternatively, ocf1a can be cleared by writing a logic one to its bit location. bit 4 ? res: reserved bit this bit is a reserved bit in the atmel ? attiny1634 and always reads as ?0?. bit 3 ? icf1: timer/counter1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm1[3:0] to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. bit 765432 1 0 0x39 (0x59) tov1 ocf1b ocf1a ? icf1 ocf0b tov0 ocf0a tifr read/write r/w r/w r/w r r/w r/w r/w r/w initial value000000 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 112 14. timer/counter prescaler timer/counter0 and timer/counter1 share the same prescaler module, but the ti mer/counters can have different prescaler settings. the description below applies to both timer/count ers. tn is used as a general name, where n = 0, 1. the fastest timer/counter operation is achieved when the timer/counter is clo cked directly by the system clock. alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock taps are: f clk_i/o /8 f clk_i/o /64 f clk_i/o /256 f clk_i/o /1024 figure 14-1 shows a block diagram of the timer/counter prescaler. figure 14-1. prescaler for timer/counter0 note: 1. the synchronization logic on the input pin ( tn) is shown in figure 14-2 on page 113 . 14.1 prescaler reset the prescaler is free running, i.e., it op erates independently of the clock select logic of the timer/counter. because the prescaler is not affected by the clock sele ction of timer/counters, the state of the prescaler has an effect where a prescaled clock is used. one example of prescaling artifacts occurs when the timer/counter is enabled while clocked by the prescaler. the time between timer/ counter enable an d the first count can be from 1 to n+ 1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). to avoid prescaling artifacts, the prescaler reset can be used for synchronizing the timer/counter with program execution. clk tn clk i/o psr10 tn 10-bit prescaler 0 csn0 ck/8 ck/64 ck/256 ck/1024 csn1 csn2 synchronization clear timer/counter clock source 113 attiny1634 [preliminary datasheet] 9296c?avr?07/14 14.2 external clock source an external clock source applied to the tn pi n can be used as the timer/counter clock (clk tn ). the pin synchronization logic samples the tn pin one time per system clock cycle. the synchronized (sampled) si gnal is then passed through the edge detector. figure 14-2 shows a block diagram of the tn synchronization and edge detector logic. figure 14-2. tn pin sampling the registers are clocked at the positiv e edge of the internal system clock (clk i/o ). the latch is transparent in the high period of the internal system clock. depending on the clock select bits of the time r/counter, the edge detector generates one clk tn pulse for each positive or negative edge it detects. the synchronization an d edge detector logic introdu ces a delay of 2.5 to 3.5 system clo ck cycles from an edge applied to the tn pin until when the counter is updated. enabling and disabling of the clock input must be done w hen tn has been stable for at least one system clock cycle, otherwise there is a risk that a false timer/counter clock pulse is generated. to ensure correct sampling, each half period of the external clock applied must be longer than one system clock cycle. given a 50/50 duty cycle, the external clock must be guarant eed to have less than half the system clock frequency (f extclk < f clk_i/o /2). because the edge detector uses sampling, the nyquis t sampling theorem states that the maximum frequency of an external clock it can detect is half the sampling frequency. howe ver, due to variatio n of the system clock frequency and duty cycle caused by oscillator source tolerances, it is recomme nded that the maximum frequency of an external clock source be less than f clk_i/o /2.5. an external clock source cannot be prescaled. 14.3 register description 14.3.1 gtccr ? general time r/counter control register bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to ?1? activates the ti mer/counter synchronization mode. in this mode, the value that is written to the psr10 bit is retained and therefore keeps the prescaler reset signal asserted. this ensures that the timer/counter is stopped and can be co nfigured without the risk of advancing during c onfiguration. when the tsm bit is written to ?0?, the psr10 bit is cl eared by the hardware and the timer/counter starts counting. bit 0 ? psr10: prescaler 0 reset timer/counter n when this bit is ?1?, the timer/counter pr escaler is reset. normally, this bit is cleared immediately by hardware, unless the tsm bit is set. tn synchronization edge detector tn_sync (to clock select logic) q le d q d q d clk i/o bit 7 6 5 4 3 2 1 0 (0x67) tsm ? ? ? ? ? ? psr10 gtccr read/write r/w r r r r r r r/w initial value 0 0 0 0 0 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 114 15. i 2 c-compatible, two-wire slave interface 15.1 features i 2 c-compatible smbus compatible (with reservations) 100khz and 400khz support at low system clock frequencies slew-rate-limited output drivers input filter provides noise suppression 7-bit and general call address recognition in hardware address mask register for address masking or dual address match 10-bit addressing supported optional software address recognition prov ides unlimited number of slave addresses operates in all sleep modes, including power-down slave arbitration allows support for smbus address resolve protocol (arp) 15.2 overview the two-wire interface (twi) is a bidi rectional, bus communication interfac e using two wires only. the twi is i 2 c-compatible and, with reservations, sm bus-compatible (see section 15.3.10 ?compatibility with smbus? on page 119 ). a device connected to the bus must act as a master or slave. the master initiates a data transaction by addressing a slave on the bus and specifying whether it wants to transmit or receive data. one bus can have several masters, and an arbitration process handles priority if two or more masters try to transmit at the same time. the twi module in atmel ? attiny1634 implements slave functionality only. lost arbitration, errors, collisions, and clock holds on the bus are detected in the hardware and indicated in separate status flags. both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a mask register for the slave address to match on a range of addresses. the slave logic cont inues to operate in all sleep modes, incl uding power-down. this enables the slave to wake up from sleep on twi address match. it is possible to disable the address matching and let this be handled in the software instead. this allows the slave to detect and respo nd to several addresses. smart mode can be enabled to auto trigger operations and reduce software complexity. the twi module includes bus state logic that collects information to detect star t and stop conditions, bus collision, and bus errors. the bus state logic continues to operate in all sleep modes including power-down. 15.3 general twi bus concepts the two-wire interface (twi) provides a simple two-wire bidirectio nal bus consisting of a serial clock line (scl) and a serial data line (sda). the two lines are open collector lines (wired-and), and pull-up resistors (rp) are the only external components needed to drive the bus. the pull-up resistors provide a high level on the lines when none of the connected devices are driving the bus. a constant current source can be used as an alternative to the pull-up resistors. the twi bus is a simple and efficient method for interconnecting multiple devices on a serial bus. a device connected to the bus can be a master or slave, with the ma ster controlling the bus and all communication. figure 15-1 on page 115 illustrates the twi bus topology. 115 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 15-1. twi bus topology a unique address is assigned to all slave devices connected to the bus and the master uses this to address a slave and initiate a data transaction. 7-bit or 10-bit addressing can be used. several masters can be connected to the same bus. this is called a multimaster environment. an arbitration mechanism is provided for resolving bus ownership between masters because on ly one master device may own the bus at any given time. a device can contain both master and slave logic and can emulat e multiple slave devices by responding to more than one address. figure 15-2 shows a twi transaction. figure 15-2. basic twi transaction diagram topology a master indicates the start of transaction by issuing a start condition (s ) on the bus. an address packet with a slave address (address) and an indica tion whether the master wishes to read or write data (r/w ) is then sent. after all data packets (data) are transferred, the mast er issues a stop condition (p) on the bus to end the transaction. the receiver must acknowledge (a) or not-acknowledge (a ) each byte received. the master provides the clock signal for t he transaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrease the clock speed. sda note: r s is optional scl v cc twi device #1 r p r p r s r s twi device #2 r s r s twi device #n r s r s sda scl the master provides data on the bus s sr/w a/ap aa address 6 ... 0 address r/w ack direction address packet data packet #0 transaction data packet #1 data ack data ack/nack 7 ... 0 7 ... 0 p data data the slave provides data on the bus the master or slave can provide data on the bus attiny1634 [preliminary datasheet] 9296c?avr?07/14 116 15.3.1 electrical characteristics the twi follows the electrical specifications and timing of i 2 c and smbus. for more information, see section 25.6 ?two-wire serial interface? on page 219 and section 15.3.10 ?compatibility with smbus? on page 119 . 15.3.2 start and stop conditions two unique bus conditions are used for marking the begi nning (start) and end (stop) of a transaction. the master issues a start condition (s) by indicating a high-to-low tr ansition on the sda line while the scl line is kept high. the master completes the transaction by issuing a stop condition (p ), indicated by a low to high transition on the sda line while the scl line is kept high. figure 15-3. start and stop conditions multiple start conditions can be issued during a single tr ansaction. a start condition not directly following a stop condition are named a repeated start condition (sr). 15.3.3 bit transfer as illustrated by figure 15-4 , a bit transferred on the sda line must be stable for the entire high period of the scl line. the sda value can thus only be changed during the low period of th e clock. this is ensured in the hardware by the twi module. figure 15-4. data validity combining bit transfers results in the forma tion of address and data packets. these pa ckets consist of eight data bits (one byte) with the most significant bit transferred first, plus a single bit not-acknowledge (nack) or acknowledge (ack) response. the addressed device signals ack by pulling the sc l line low and nack by leaving the line scl high during the ninth clock cycle. 15.3.4 address packet after the start condition, a 7-bit address followed by a read/write (r/w ) bit is sent. this is always transmitted by the master. a slave recognizing its address acknowledges the addre ss by pulling the data line low the next scl cycle, while all other slaves should keep the twi lines released and wait for the next start and address. the address packet consists of the combined 7-bit address, the r/w bit, and the acknowledge bit. only one address packet for each start condition is given, even if 10-bit addressing is used. the r/w specifies the direction of the transaction. if the r/w bit is low, it indicates a master write transaction and the master transmits its data after the slave has acknowledged its address. conversely, for a master read operation the slave starts to transmit data after acknowledging its address. sda s start condition scl p stop condition data valid change allowed sda scl 117 attiny1634 [preliminary datasheet] 9296c?avr?07/14 15.3.5 data packet data packets succeed an address packet or another data packet. all data packets are nine bits long, consisting of one data byte and an acknowledge bit. the direction bit in the previous address packet determines the direction in which the data is transferred. 15.3.6 transaction a transaction is the co mplete transfer from a start to a stop condition including any repeated start conditions in between. the twi standard defines three fundamental transaction modes: master write, master read, and combined transaction. figure 15-5 illustrates the master write transact ion. the master initiates the transac tion by issuing a start condition (s) followed by an address packe t with direction bit set to ?0? (address+w ). figure 15-5. master write transaction given that the slave acknowledges the address, the master ca n start transmitting data (data) and the slave will ack or nack (a/a ) each byte. if no data pa ckets are to be transmitted, the master term inates the transaction by issuing a stop condition (p) directly after the address packet. there are no limitations to the number of data packets that can be transferred . if the slave signals a nack to the data, the master must assume that the slav e cannot receive any more data and thus terminates the transaction. figure 15-6 illustrates the master read transaction. the master initiates the transaction by issuing a start condition followed by an address packet with the direction bit set to ?1? (adress+r). the addressed slave must acknowledge the address for the master to be allowed to continue the transaction. figure 15-6. master read transaction provided the slave acknowledges the address, the master can st art receiving data from the slave. there are no limitations to the number of data packets that can be transferred. the slav e transmits the data while t he master signals ack or nack after each data byte. the master terminates the trans fer with a nack before issuing a stop condition. figure 15-7 illustrates a combined tran saction. a combined transaction consists of several read and write transactions separated by a repeated start conditions (sr). figure 15-7. combined transaction a p a/a address packet data packet n data packets transaction swa address data data a p a address packet data packet n data packets transaction sra address data data address packet #1 n data packet direction address packet #2 n data packet transaction sr sr/wa a p address address data data direction r/w a/a a/a attiny1634 [preliminary datasheet] 9296c?avr?07/14 118 15.3.7 clock and clock stretching all devices connected to the bus are allowed to stretch the lo w period of the clock to slow down the overall clock frequency or to insert wait states while processing data. a device that needs to stretch the cl ock can do this by holding/forcing the scl line low after it detects a low level on the line. three types of clock stretching can be defined as shown in figure 15-8 . figure 15-8. clock stretching if the device is in sleep mode and a start condition is detect ed, the clock is stretched duri ng the wake-up period for the device. a slave device can slow down the bus frequency by stretching the clock periodically at the bit level. this allows the slave to run at a lower system clock frequency. however, the overall performance of the bus is correspondingly reduced. both the master and slave device can randomly stretch the clock at the by te level before and after the ack/nack bit. this provides time to process incoming data , prepare outgoing data, or perform other time-critical tasks. if the slave is stretching the clock, the master is forced into a wait state until the slave is ready and vice versa. 15.3.8 arbitration a master can only start a bus transaction if it has detected that the bus is idle. because the twi bus is a multimaster bus, two devices may initiate a transaction at the same time. this re sults in multiple masters owning the bus simultaneously. this is solved using an arbitration scheme where th e master loses control of t he bus if it is not able to transmit a high level on t he sda line. the masters which lose arbitratio n must then wait until the bus becomes id le (i.e., wait for a stop condition) before attempting to reacquire bus ownership. slave de vices are not involved in the arbitration procedure. figure 15-9. twi arbitration figure 15-9 shows an example where two twi masters are contending for bus ownership. both devices are able to issue a start condition, but device1 loses arbitration when attempti ng to transmit a high level (bit 5) while device2 is transmitting a low level. sda scl bit 7 s bit 6 bit 0 ack/nack period clock stretching wake-up clock stretching random clock stretching device1_sda scl device2_sda sda (wired-and) device1 loses arbitration bit 7 bit 6 bit 5 bit 4 s 119 attiny1634 [preliminary datasheet] 9296c?avr?07/14 arbitration between a repeated start condition and a data bi t, between a stop condition and a data bit, or between a repeated start condition and stop condition are not a llowed and require special handling by the software. 15.3.9 synchronization a clock synchronization algorithm is necessary for solving situat ions where more than one master is trying to control the scl line at the same time. the algorithm is based on the same pr inciples used for clock stretching described in the previous section. figure 15-10 shows an example where two masters are competing for control over the bus clock. the scl line is the wired-and result of the two masters? clock outputs. figure 15-10.clock synchronization a high-to-low transition on the scl line forces the line low for all masters on the bus and all masters start timing their low clock period. the timing length of the low clock period can vary among the masters. when a master (device1 in this case) has completed its low period, it releases the scl line. howeve r, the scl line does not go high before all masters have released it. as a result, the scl line is held low by the device with the longest low period (device2). devices with shorter low periods must insert a wait state until the clock is rel eased. all masters start their high period when the scl line is released by all devices and has become high. the device which fi rst completes its high period (device1) forces the clock line low and the procedure is then repeated. th e result is that the device with the s hortest clock period determines the high period while the low period of the clock is determined by the longest clock period. 15.3.10 compatibility with smbus as with any other i 2 c-compliant interface, there are known compatibilit y issues designers should be aware of before connecting a twi device to smbus devices. the follo wing should be noted for use in smbus environments: all i/o pins of an avr ? , including those of the two-wire interface, ha ve protection diodes to both supply voltage and ground (see figure 11-1 on page 53 ). this is in contradiction to the requi rements of the smbus specifications. as a result, supply voltage must never be removed from the av r or the protection diodes will pull the bus lines down. power-down and sleep modes are not a problem, provided supply voltages remain. the data hold time of the twi is lower than specified for smbus. smbus has a low speed limit, while i 2 c does not. as a master in an smbus environment, the avr must ensure that the bus speed does not drop below specifications because lower bus speeds trigger time-outs in smbus slaves. if the avr is configured, a slave there may cause a bus locku p because the twi module does not identify time-outs. device1_scl device2_scl scl (wired-and) low period count wait state high period count attiny1634 [preliminary datasheet] 9296c?avr?07/14 120 15.4 twi slave operation the twi slave is byte-oriented with optional interrupts after each byte. there are separate interrupt flags for data interrupt and address/stop interrupt. interrupt flags can be set to trigge r the twi interrupt, or be used for polled operation. there are dedicated status flags for indicating ack/nack received, clo ck hold, collision, bus error, and read/write direction. when an interrupt flag is set, the scl line is forced low. this gives the slave time to respond or handle any data and most cases requires software interaction. figure 15-11 . shows the twi-slave operation. the diamond-shaped symbols (sw) indicate where software interaction is required. figure 15-11.twi slave operation the number of interrupts generated is kept to a minimum by au tomatic handling of most conditions. quick commands can be enabled to auto trigger operations and reduce software complexity. promiscuous mode can be enabled to allow the slave to respond to all received addresses. 15.4.1 receiving address packets when the twi slave is properly confi gured, it waits for a start condition to be detected. when this happens, the successive address byte is received and checked by the addre ss match logic and the slave will ack the correct address. if the received address is not a match, the slave does not acknowledge the address and waits for a new start condition. the slave address/stop interrupt flag is set when a start c ondition followed by a valid address packet is detected. a general call address also sets the interrupt flag. a start condition immediately followed by a stop condition is an illegal operation and the bus error flag is set when this happens. the r/w direction flag reflects the directio n bit received with the address. this can be read by software to determine the type of operation currently in progress. depending on the r/w direction bit and bus cond ition, one of four distinct cases (1 to 4) arises following the address packet. the different cases must be handled in software. 15.4.1.1 case 1: address packet accepted ? direction bit set if the r/w direction flag is set, this indicates a master read operati on. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave har dware sets the data interrupt flag indicating data is needed for transmit. if nack is sent by the slave, the slave waits for a new start condition and address match. 15.4.1.2 case 2: address packet accepted ? direction bit cleared if the r/w direction flag is cleared, this indicates a master writ e operation. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave waits for data to be received. data, repeated start or stop can be received after this. if nack is indicated, the slave wa its for a new start condition and address match. address driver software driver software the master provides data on the bus slave provides data on the bus interrupt on stop condition enabled release hold data ra a ssw s3 a a s1 s1 slave address interrupt slave data interrupt wa a sr p sw sw sw sw sw sw a/a s1 s1 s2 sn s2 s3 data sr p s2 s3 s1 collision (smbus) 121 attiny1634 [preliminary datasheet] 9296c?avr?07/14 15.4.1.3 case 3: collision if the slave is not able to send a high level or nack, the colli sion flag is set and it disables the data and acknowledge outpu t from the slave logic. the clock hold is released . a start or repeated start condition is accepted. 15.4.1.4 case 4: stop condition received operation is the same as case 1 or 2 above with one exception: when the st op condition is received, the slave address/stop flag is set, indicating that a st op condition occurred, not an address match. 15.4.2 receiving data packets the slave knows when an address packet with the r/w direction bit cleared has been successfully received. after acknowledging this, the slave must be ready to receive data. when a data packet is received, the data interrupt flag is set and the slave must indicate ack or nack. after indicating a nack, the slave must expect a stop or repeated start condition. 15.4.3 transmitting data packets the slave knows when an address packet with the r/w direction bit set has been successfully received. it can then start sending data by writing to the slave data register. when a dat a packet transmission has been completed, the data interrupt flag is set. if the master indicates nack, the slave must stop transmitting data and expect a stop or repeated start condition. 15.5 register description 15.5.1 twscra ? twi slave control register a bit 7 ? twshe: twi sda hold time enable when this bit is set, each negative transition of scl triggers an additional internal delay before the device is allowed to change the sda line. the added delay is approximately 50ns in length. this may be useful in smbus systems. bit 6 ? res: reserved bit this bit is reserved and always reads as ?0?. bit 5 ? twdie: twi data interrupt enable when this bit is set and interrupts are enabled, a twi interrupt is generated when the data interrupt flag (twdif) in twssra is set. bit 4 ? twasie: twi address/stop interrupt enable when this bit is set and interrupts are enabled, a twi interrupt is generated when the address/ stop interrupt flag (twasif) in twssra is set. bit 3 ? twen: two-wire interface enable when this bit is set, the slave two-wire interface is enabled. bit 2 ? twsie: twi stop interrupt enable setting the stop interrupt enable (twsie) bit sets the twasif in the twssra register when a stop condition is detected. bit 1 ? twpme: twi promiscuous mode enable when this bit is set, the address match logic of the slave tw i responds to all received addresses. when this bit is cleared, the address match logic uses the twsa register to determine which address to recognize as its own. bit 76543210 (0x7f) twshe ? twdie twasie twen twsie twpme twsme twscra read/write r/w r r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 122 bit 0 ? twsme: twi smart mode enable when this bit is set, the twi slave ent ers smart mode where the acknowledge action is sent immediately after the twi data register (twsd) has been read. acknowledge ac tion is defined by the twaa bit in twscrb. when this bit is cleared the acknowledge action is s ent after twcmdn bits in twscrb are written to 1x. 15.5.2 twscrb ? twi slave control register b bits 7:3 ? res: reserved bits these bits are reserved and always read as ?0?. bit 2 ? twaa: twi acknowledge action this bit defines the slave's acknowledge behavior after an address or data byte has been received from the master. depending on the twsme bit in twscra, the acknowledge action is executed either when a valid command has been written to twcmdn bits or when the data register has been read. acknowledge acti on is also executed if the twaif flag is cleared after an address match or the twdif flag is cleared during master transmit (see table 15-1 ). bits 1:0 ? twcmd[1:0]: twi command writing these bits triggers the slave operation as defined in table 15-2 . the type of operation depends on the twi slave interrupt flags, twdif and twasif. the acknowledge action is only executed when the slave receives data bytes or address bytes from the master. bit 76543210 (0x7e) ? ? ? ? ? twaa twcmd1 twcmd0 twscrb read/write r r r r r r/w w w initial value00000000 table 15-1. acknowledge action of twi slave twaa action twsme when 0 send ack 0 when twcmdn bits are written to ?10? or ?11? 1 when twsd is read 1 send nack 0 when twcmdn bits are written to ?10? or ?11? 1 when twsd is read table 15-2. twi slave command twcmd[1:0] twdir operation 00 x no action 01 x reserved 10 used to complete transaction 0 execute acknowledge action, then wait for any start (s/sr) condition 1 wait for any start (s/sr) condition 11 used in response to an address byte (twasif is set) 0 execute acknowledge action, then receive next byte 1 execute acknowledge action, then set twdif used in response to a data byte (twdif is set) 0 execute acknowledge action, then wait for next byte 1 no action 123 attiny1634 [preliminary datasheet] 9296c?avr?07/14 writing the twcmd bits automatically releases the scl line and clears the twch and slave interrupt flags. twaa and twcmdn bits can be written at the same time. acknowledge action is then exec uted before the command is triggered. the twcmdn bits are strobed and always read as ?0?. 15.5.3 twssra ? twi slave status register a bit 7 ? twdif: twi data interrupt flag this flag is set when a data byte has been successfully rece ived, i.e., no bus errors or collisions have occurred during the operation. when this flag is set, the slave forces the scl line low, stretching the twi clock per iod. the scl line is released by clearing the interrupt flags. writing a ?1? to this bit clears the flag. this flag is also automatically cleared when writing a valid command to the twcmdn bits in twscrb. bit 6 ? twasif: twi address/stop interrupt flag this flag is set when the slave detects that a valid addr ess has been received or when a transmit collision has been detected. when this flag is set, the slave forces the scl line low, stretching the twi clock period. the scl line is released by clearing the interrupt flags. if twasie in twscra is set, a stop condition on the bus al so sets twasif. a stop condition sets the flag only if the system clock is faster than the minimum bus free time between stop and start. writing a ?1? to this bit clears the flag. this flag is also automatically cleared when writing a valid command to the twcmdn bits in twscrb. bit 5 ? twch: twi clock hold this bit is set when the slave is holding the scl line low. this bit is read-only and set when twdif or twasif is set. th e bit can be cleared indirectly by clearing the interrupt flags and releasing the scl line. bit 4 ? twra: twi receive acknowledge this bit contains the most recently re ceived acknowledge bit from the master. this bit is read-only. when ?0?, the most recent acknowledge bit from the master was ack and, when ?1?, the most recent acknowledge bit was nack. bit 3 ? twc: twi collision this bit is set when the slave is unable to transfer a high data bit or a nack bit. when a collision is detected, the slave commences normal operation and disables data and acknowledges output. no low values are shifted out onto the sda line. this bit is cleared by writing a ?1? to it. the bit is also cl eared automatically when a start or repeated start condition is detected. bit 2 ? twbe: twi bus error this bit is set when an illegal bus condition has occurred dur ing a transfer. an illegal bus condition occurs if a repeated start or stop condition is detected and the number of bits fr om the previous start condition is not a multiple of nine. this bit is cleared by writing a ?1? to it. bit 1 ? twdir: twi r ead/write direction this bit indicates the direction bit from the last address packet received from a master. when this bit is ?1?, a master read operation is in progress. when the bit is ?0 ?, a master write operation is in progress. bit 76543210 (0x7d) twdif twasif twch twra twc twbe twdir twas twssra read/write r/w r/w r r r/w r/w r r initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 124 bit 0 ? twas: twi address or stop this bit indicates why the twasif bit was last set. if ?0?, a st op condition caused twasif to be set. if ?1?, address detection caused twasif to be set. 15.5.4 twsa ? twi slave address register the slave address register contains the twi slave address used by the slave address match logic to determine if a master has addressed the slave. when using 7-bit or 10-bit address re cognition mode, the high seven bits of the address register (twsa[7:1]) represent the slave address. the least signific ant bit (twsa0) is used for general call address recognition. setting twsa0 enables general call address recognition logic. when using 10-bit addressing, the address match logic only suppor ts hardware address recognition of the first byte of a 10- bit address. if twsa[7:1] is set to ?0b11110nn?, ?nn? represents bits 9 and 8 of the slave addr ess. the next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software. when the address match logic detects that a valid address by te has been received, the twasif is set and the twdir flag is updated. if twpme in twscra is set, the address match logic responds to all addresses transmitted on the twi bus. twsa is not used in this mode. 15.5.5 twsd ? twi slave data register the data register is used when transmitting and receiving data. during transfer, data is shif ted from/to the twsd register and to/from the bus. the data register thus cannot be accessed during byte transfers. this is protected in the hardware. the data register can only be accessed when the scl line is held low by the slave, i.e., when twch is set. when a master reads data from a slave, the data to be sent must be written to the twsd register. the byte transfer is started when the master starts to clock th e data byte from the slave. it is follow ed by the slave receiving the acknowledge bit from the master. the twdif and the twch bits are then set. when a master writes data to a slave, the twdif and the twch flags are set when one byte has been received in the data register. if smart mode is enabled, reading the data register tr iggers the bus operation as set by the twaa bit in twscrb. accessing twsd clears the slave interrupt flags and the twch bit. bit 76543210 (0x7c) twsa[7:0] twsa read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x7a) twsd[7:0] twsd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 125 attiny1634 [preliminary datasheet] 9296c?avr?07/14 15.5.6 twsam ? twi slave address mask register bits 7:1 ? twsam[7:1]: twi address mask depending on the twae setting, these bits can act as a seco nd address match register or an address mask register. if twae is set to ?0?, twsam can be loaded with a 7-bit sl ave address mask. each bit in twsam can mask (disable) the corresponding address bit in the twsa register. if the mask bi t is ?1?, the address match between the incoming address bit and the corresponding bit in twsa is ignored. in other words, masked bits always match. if twae is set to ?1?, twsam can be loaded with a second slav e address in addition to the twsa register. in this mode, the slave matches at two unique addresses, one in twsa and the other in twsam. bit 0 ? twae: twi address enable by default, this bit is ?0? and the twsam bits act as an address mask to the twsa register. if this bit is set to ?1?, the slav e address match logic responds to the two unique addresses in twsa and twsam. bit 76543210 (0x7b) twsam[7:1] twae twsam read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 126 16. usi ? universal serial interface 16.1 features two-wire synchronous data transfer (master or slave) three-wire synchronous data transfer (master or slave) data received interrupt wake-up from idle mode in two-wire mode: wake-up from all sleep modes including power-down mode two-wire start condition detector with interrupt capability 16.2 overview the universal serial interface (usi) provides basic hardware resources for serial communicati on. combined with a minimum of control software, the usi allows sign ificantly higher transfer rates and uses less code space than solutions based on software alone. the usi hardware also includes interrupts to minimize the processor load. a simplified block diagram of the usi is shown in figure 16-1 . figure 16-1. universal serial interface, block diagram incoming and outgoing data is contained in the 8-bit usi data register (usidr). it is directly accessible via the data bus, but a copy of the contents is also placed in the usi buffer regist er (usibr) where it can be retrieved later. if usidr is read directly, it must be done as quickly as possible to ensure that no data is lost. depending on the operating mode, the most significant bit of us idr is connected to one of two output pins. a transparent latch between the output of usidr and the output pin delays the change of data output to the opposite clock edge of the data input sampling. regardless of the operating mode, the serial input is always sampled from the data input (di) pin. the 4-bit counter can be read and writte n via the data bus and can generate an overflow interrupt. both usidr and the counter are clocked simultaneously by the sa me clock source. this allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. q 3 2 1 0 le 2 usidr d tim0 comp usck/ scl two-wire clock control unit clock hold data bus [1] bit0 bit7 usisif usioif usipf usidc usibr usisr 4-bit counter di/ sda do (output only) (input/ open drain)) (input/ open drain)) 3 2 1 0 1 0 usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr 127 attiny1634 [preliminary datasheet] 9296c?avr?07/14 when an external clock source is select ed, the counter counts both clock edges, meaning it regi sters the number of clock edges and not the number of data bits. the clock can be selected from three different sources: the usck pin the timer/counter0 compare match the software the two-wire clock control unit can be configured to generat e an interrupt when a start co ndition has been detected on the two-wire bus. by holding the clock pin low after a start condition is detected or after the coun ter overflows, the unit can als o be used to generate wait states. the usi connects to i/o pins of the device as listed in table 16-1 . for i/o pin placement, see section 1-1 ?pinout of atmel attiny1634? on page 3 . the device-specific i/o register and bit locations are listed in section 16.7 ?register descriptions? on page 133 . 16.3 three-wire mode the usi three-wire mode complies with the serial peripheral interface (spi) mode 0 and 1 but does not have slave select (ss) pin functionality. however, this feature can be implement ed in software if necessary. pin names used in this mode are di, do, and usck (see table 16-1 ). figure 16-2 shows two usi units operating in three-wire mode, one as master and one as slave. the two usi data registers are interconnected in such a wa y that after eight usck clocks, the data in each register has been interchanged. the same clock also increments the usi?s 4-bit counter. the counter ov erflow (interrupt) flag, or usioif, can thus be used to determine when a transfer has been completed. the clock is g enerated via the master device software by toggling the usck pin or by writing a ?1? to the usitc bit in usicr. figure 16-2. three-wire mode op eration, simplified diagram table 16-1. usi connects to i/o pins of the device three-wire mode two-wire mode pin data input (di) serial data (sda) pb1 data output (do) ? pb2 clock (usck) serial clock (scl) pc1 bit7 di usck usck do portxn slave bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 di do master bit6 bit5 bit4 bit3 bit2 bit1 bit0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 128 the three-wire mode timing is shown in figure 16-3 . at the top of the figure is a usck cycle referenc e. one bit is shifted into the usi data register (usidr) for each of these cycles. the usck timing is shown for both exte rnal clock modes. in external clock mode 0 (usics0 = 0) di is sampl ed at positive edges and do is changed (usi dr is shifted by one) at negative edges. in external clock mode 1 (usics0 = 1) th e opposite edges are used. in other words, data is sampled at negative and output is changed at positive edges. the usi clock modes correspond to the spi data mode 0 and 1. figure 16-3. three-wire mode, timing diagram as shown in the timing diagram in figure 16-3 , a bus transfer involves the following steps: 1. the slave and master devices set up their data outputs and, depending on the protocol used, enable their output drivers (mark a and b). the output is se t up by writing the data to be transm itted to usidr. t he output is enabled by setting the bit corresponding to do in the data direction register (ddrx) of the port. note that there is not a pre- ferred order of points a and b in the figure; both must be at least one-half usck cycle before point c, where the data is sampled. this is in order to ensure that the data se tup requirement is satisfied. the 4-bit counter is reset to ?0?. 2. the master software generates a clock pulse by toggling the usck line twice (c and d). the bit value on the data input pin (di) is sampled by the usi on the first edge (c) and the data output is changed on the opposite edge (d). the 4-bit counter counts both edges. 3. step 2 is repeated eight times for a complete register (byte) transfer. 4. after eight clock pulses (i.e., 16 clock edges) the coun ter overflows and indicates that the transfer has been com- pleted. if usi buffer registers are not used, the data bytes that have been transferred must now be processed before a new transfer can be in itiated. the overflow interrupt wakes up t he processor if it is set to idle mode. depending on the protocol used, the slave devic e can now set its output to high impedance. 16.4 two-wire mode the usi two-wire mode complies with the in ter ic (twi) bus protocol, but without slew rate limit ing on outputs and without input noise filtering. pin names used in this mode are scl and sda (see table 16-1 on page 127 ). figure 16-4 on page 129 shows two usi units operating in two-wire mode, one as master and one as slave. only the physical layer is shown because the system operation highly depends on the communication scheme used. the main differences between the master and slave op eration at this level is the serial cl ock generation which is always done by the master. only the slave uses the clock control unit. 12 6 msb 54321lsb 345678 6 msb cycle (reference) usck usck 54321lsb a b c d e di do 129 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 16-4. two-wire mode operation, simplified diagram clock generation must be implemented in the software; but the shift operation is done automatically in both devices. note that clocking only on negative edges for shif ting data is of practical use in this mode. the slave can insert wait states at th e start or end of transfer by forcing the scl clock low. this me ans the master must always check if the scl line was actually released after it has generated a positive edge. because the clock also increments the counter, a counter over flow can be used to indicate that the transfer has been completed. the clock is generated by the master by toggling the usck pin via the port register. the data direction is not given by the physical layer. a protoc ol, such as the one used by the twi bus, must be implemented to control data flow. figure 16-5. two-wire mode, typical timing diagram bit7 sda scl hold scl slave bit6 bit5 bit4 bit3 bit2 bit1 bit0 two-wire clock control unit vcc bit7 sda scl master bit6 bit5 bit4 bit3 bit2 bit1 bit0 portxn 1 to 7 8 s address r/w ack data ack ack data 1 to 8 9 1 to 8 9 9 a b c d e f sda scl p attiny1634 [preliminary datasheet] 9296c?avr?07/14 130 as shown in the timing diagram ( figure 16-5 ), a bus transfer involves the following steps: 1. the start condition is generated by the master by forc ing the sda low line while keeping the scl line high (a). sda can be forced low either by writing a ?0? to bit 7 of usidr or by setting the corresponding bit in the port register to ?0?. note that the data direction register (ddrx) bit must be se t to ?1? for the output to be enabled. the start detector logic of the slave device (see figure 16-6 on page 130 ) detects the start condition and sets the usisif flag. the flag can generat e an interrupt where required. 2. the start detector holds the scl line low after the master has forced a negative edge on this line (b). this allows the slave to wake up from sleep or co mplete other tasks before se tting up usidr to receive the address. this is done by clearing the start condition flag and resetting the counter. 3. the master sets the first bit to be transferred and releas es the scl line (c). the slave samples the data and shifts it into usidr at the positive edge of the scl clock. 4. after eight bits containing slave address and data dire ction (read or write) have b een transferred, the slave coun- ter overflows and the scl line is forced low (d). if the sl ave is not the one the master has addressed, it releases the scl line and waits for a new start condition. 5. when the slave is addressed, it holds the sda line lo w during the acknowledgment cycle before holding the scl line low again (i.e., the usi counter register must be set to ?14? before releasing scl at (d)). the master or slave enables its output depending on the r/w bit. if the bit is se t, a master read operation is in progress (i.e., the slave drives the sda line). the slave can hold the scl line low after the acknowledgment (e). 6. multiple bytes can now be transmitted?all in the same di rection?until a stop condition is given by the master (f) or a new start condition is given. if the slave is not able to receive more data, it does not acknowledge the data by te it has last received. when the master does a read operation, it must terminate the operation by forcing the acknowledge bi t low after the last byte transmitted. 16.4.1 start condition detector the start condition detector is shown in figure 16-6 . the sda line is delayed (in the range of 50ns to 300ns) to ensure valid sampling of the scl line. the start condition de tector is only enabled in two-wire mode. figure 16-6. start condition detector, logic diagram the start condition detector works asynchronously and can t herefore wake up the processor from power-down sleep mode. however, the protocol used might have rest rictions on the scl hold time. as a result, when using this feature, the oscillator start-up time (set by cksel fuses, see section 7.2 ?clock sources? on page 26 ) must also be considered. for more information, see the description of the usisif bit in section 19. ?analog comparator? on page 169 . 16.4.2 clock speed considerations maximum frequency for scl and sck is f ck /2. this is also the maximum data trans mit and receive rate in both two- and three-wire mode. in two-wire slave mode the two-wire clock control unit holds the scl low until t he slave is ready to receive more data. this may reduce the cu rrent data rate in two-wire mode. q sda scl write (usisif) d clr q d usisif clock hold clr 131 attiny1634 [preliminary datasheet] 9296c?avr?07/14 16.5 alternative use the flexible design of the usi allows it to be used for other tasks when serial communication is not needed. some examples are given below. 16.5.1 half-duplex asynchronous data transfer a more compact and higher performance uart can be implemented than through using software only by using the usi data register in three-wire mode. 16.5.2 4-bit counter the 4-bit counter can be used as a stand-alo ne counter with overflow interrupt. note t hat if the counter is clocked externally, both clock edges increm ent the counter value. 16.5.3 12-bit timer/counter combining the 4-bit usi counter with one of the 8-bit timer/coun ters creates a 12-bit counter. 16.5.4 edge-triggered external interrupt the counter can function as an additional external interrupt by setting it to ma ximum value (f). the overflow flag and interrupt enable bit are then used for the external in terrupt. this feature is selected by the usics1 bit. 16.5.5 software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 16.6 program examples 16.6.1 example: spi master operation the following code demonstrates how to use the usi module as an spi master. see section 4.2 ?code examples? on page 7 . the code is size-optimized using only eight instructions (p lus return). the code example assumes that the do and usck pins have been enabled as outputs in the data direction register (ddrx). the value stor ed in register r16 before the function is called is transferred to the slave device and when the transf er is completed, the data received from the slave is stored back in register r16. the first two instructions clear the usi counter overflow flag and the usi counter value. the next two instructions set three- wire mode, positive edge clock, count at usitc strobe, and toggle usck. the transfer loop is then repeated 16 times. assembly code example spitransfer: out usidr,r16 ldi r16,(1< attiny1634 [preliminary datasheet] 9296c?avr?07/14 134 bits 3:2 ? usics[1:0]: clock source select these bits set the clock source for the usi data register and counter. the data output latc h ensures that the output is changed at the opposite edge of the sampling of the data input (di/sda) when using an external clock source (usck/scl). when software strobe or timer/counter0 compare match clock op tion is selected, the output latch is transparent and the output is therefore changed immediately. clearing the usics[1:0] bits enables the software strobe option. when using this option, writing a ?1? to the usiclk bit clocks both the usi data register and the counter. for ex ternal clock source (usics1 = 1), t he usiclk bit is no longer used as a strobe, instead it selects be tween external clocking or software clocking by the usitc strobe bit. table 16-3 shows the relationship between the usics[1:0] and usiclk setting and clock source used for the usi data register and the 4-bit counter. bit 1 ? usiclk: clock strobe writing a ?1? to this bit location strobes the usi data register to shift one step and the counter to increment by one, provide d that the software clock strobe option has been selected by writ ing usics[1:0] bits to ?0?. the output immediately changes when the clock strobe is executed, i.e., du ring the same instruction cycle. the value shifted into the usi data register is sampled in the previo us instruction cycle. when an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. in this case, setting the usiclk bit selects the usitc strobe bit as a clock source fo r the 4-bit counter (see table 16-3 ). the bit is read as ?0?. bit 0 ? usitc: toggle clock port pin writing a ?1? to this bit location toggles the usck/scl value eith er from ?0? to ?1?, or from ?1? to ?0?. the toggling does not depend on the setting in the data direction register; however, if the port value is to be shown on the pin, the corresponding ddr pin must be set as output (to ?1?). this feature allo ws easy clock generation when implementing master devices. when an external clock source is selected (usics1 = 1) and th e usiclk bit is set to ?1?, writing to the usitc strobe bit clocks the 4-bit counter directly. this allo ws early detection of when the transfer is done when operating as a master device. the bit reads as ?0?. table 16-3. relationship between the usics1:0 and usiclk setting usics1 usics0 usiclk clock source 4-bit counter clock source 0 0 0 no clock no clock 0 0 1 software clock strobe (usiclk) software clock strobe (usiclk) 0 1 x timer/counter0 compare match a timer/counter0 compare match 1 0 0 external, positive edge external, both edges 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge software clock strobe (usitc) 1 1 1 external, negative edge software clock strobe (usitc) 135 attiny1634 [preliminary datasheet] 9296c?avr?07/14 16.7.2 usisr ? usi status register the status register contains interrupt flags, line status flags, and the counter value. bit 7 ? usisif: start condition interrupt flag when two-wire mode is selected, the usisif flag is set (to ?1 ?) when a start condition has been detected. when three-wire mode or output disable mode has been select ed, any edge on the sck pin sets the flag. if the usisie bit in usicr and the global interrupt enable flag are set, an interrupt is generated when this flag is set. the f lag is only cleared by writing a logic one to the usisif bit. clear ing this bit releases the start detection hold of uscl in two-wi re mode. a start condition interrupt wakes up the processor from all sleep modes. bit 6 ? usioif: counter overflow interrupt flag this flag is set (?1?) when the 4-bit counter overflows (i.e., at the transition from ?15? to ?0?). if the usioie bit in usicr and the global interrupt enable flag are set, an interrupt is also generated when the flag is set. the flag is only cleared if a ?1 ? is written to the usioif bit. clearing this bit releases the counter overflow hold of scl in two-wire mode. a counter overflow interrupt wakes up the processor from idle sleep mode. bit 5 ? usipf: stop condition flag when two-wire mode is selected, the usipf flag is set (?1?) when a stop condition has been detected. this flag is cleared by writing a ?1? to this bit. note that this is not an interrupt flag. this signal is useful when implementing two-wire bus master arbitration. bit 4 ? usidc: data output collision this bit is logic one when bit 7 in the usi data register differ s from the physical pin value. the flag is only valid when two- wire mode is used. this signal is useful when im plementing two-wire bus master arbitration. bits 3:0 ? usicnt[3 :0]: counter value these bits reflect the current 4-bit count er value. the 4-bit counter value can be read or written by the cpu directly. the 4-bit counter increments by one for each clock generat ed either by the external clock edge detector, by a timer/counter0 compare ma tch, or by software using usiclk or usitc strobe bits. the clock source depends on the setting of the usics[1:0] bits. for external clock operation a special feature is added that a llows the clock to be generated by writing to the usitc strobe bit. this feature is enabled by choosing an external clock source (usics1 = 1) and writing a ?1? to the usiclk bit. note that even when no wire mode is selected (usiwm[1 : 0] = 0), the external clock input (usck/scl) can still be used by the counter. bit 7 6 5 4 3 2 1 0 0x2b (0x4b) usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 usisr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 136 16.7.3 usidr ? usi data register the usi data register can be accessed di rectly but a copy of the data can al so be found in the usi buffer register. depending on the usics[1:0] bits of the usi control register, a (left) shift operation may be performed. the shift operation can be synchronized to an external clock edge, to a timer/counte r0 compare match, or directly to software via the usiclk bit. if a serial clock occurs in the same cycle the register is written, the register contains the value written and no shift i s performed. note that even when no wire mode is selected (usiwm[1:0] = 0), both the external data input (di/sda) and the external clock input (usck/scl) can still be used by the usi data register. the output pin (do or sda, depending on th e wire mode) is connected via the output latch to the most significant bit (bit 7) of the usi data register. the output latc h ensures that data input is sampled a nd data output is changed on opposite clock edges. the latch is open (transpar ent) during the first half of a serial clock cycl e while an external clock source is selected (usics1 = 1) and constantly open when an internal clock sour ce is used (usics1 = 0). the output is changed immediately when a new msb is written as long as the latch is open. note that the data direction register bit corresponding to the out put pin must be set to ?1? in order to enable data output fro m the usi data register. 16.7.4 usibr ? usi buffer register instead of reading data from the usi data register, the usi buffer register can be used. this makes controlling the usi less time-critical and give s the cpu more time to handle other program tasks. us i flags are set in a way similar to when reading the usidr register. the content of the usi data register is loaded to the usi buffer register when the transfer has been completed. bit 7 6 5 4 3 2 1 0 0x2c (0x4c) msb lsb usidr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 0x2d (0x4d) msb lsb usibr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 137 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17. usart (usart0 and usart1) 17.1 features full duplex operation (independent serial receive and transmit registers) asynchronous or synchronous operation master- or slave-clocked synchronous operation high-resolution baud rate generator supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits odd or even parity generation and parity check supported by hardware data overrun detection framing error detection noise filtering includes false start bit detection and digital low pass filter three separate interrupts on tx complete, tx data register empty, and rx complete multiprocessor communication mode double-speed asynchronous communication mode start frame detection 17.2 usart0 and usart1 the atmel ? attiny1634 has two universal synchronous and asynchronous serial receiver and transmitters?usart0 and usart1. the functionality for all usarts is described below; most regi ster and bit references in this section are written in general form. a lowercase ?n? replaces the usart number. as shown in section 27. ?register summary? on page 245 , usart0 and usart1 have different i/o registers. 17.3 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. a simplified block diagram of the usart transmitter is shown in figure 17-1 on page 138 . cpu-accessible i/o registers and i/o pins are shown in bold. the power reduction usart0 bit, prusart0, in section 8.4.2 ?prr ? power reduction register? on page 37 must be disabled by writing a logic zero to it. the power reduction usart1 bit, prusart1, in section 8.4.2 ?prr ? power reduction register? on page 37 must be disabled by writing a logic zero to it. attiny1634 [preliminary datasheet] 9296c?avr?07/14 138 figure 17-1. usart block diagram for usart pin placement, see figure 1-1 on page 3 and section 11.3 ?alternate port functions? on page 59 . the dashed boxes in the block diagram of figure 17-1 illustrate the three main parts of t he usart as follows (listed from the top): clock generator transmitter receiver the clock generation logic consists of synchronization logic (for external clock input in synchronous slave operation) and the baud rate generator. the transfer clock pin (xckn) is only used in synchronous transfer mode. the transmitter consists of a single write buffer, a serial sh ift register, a parity generator, and control logic for handling different serial frame formats. the wr ite buffer allows a continuous transfe r of data without delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recove ry units, the receiver includes a parity checker, control logic, a shift register, and a two-level receive buffer (udrn). the re ceiver supports the same frame formats as the transmitter and can detect the following errors: frame error data overrun error parity errors transmit shift register receive shift register data recoverc clock recoverc parity checker parity generator pin control tx control pin control pin control rx control udr (transmit) transmitter clock generator receiver ucsra sync logic osc udr (receive) data bus baud rate generator ubrr[h:l] xck rxd txd ucsrb ucsrc ucsrd 139 attiny1634 [preliminary datasheet] 9296c?avr?07/14 the usartn power reduction bit must be disabled for the usart to operate (see section 8.4.2 ?prr ? power reduction register? on page 37 ). 17.4 clock generation the clock generation logic creates the base clock for the tran smitter and receiver. a block diagram of the clock generation logic is shown in figure 17-2 . figure 17-2. clock generati on logic, block diagram signal description for figure 17-2 : txclk transmitter clock (internal signal) rxclk receiver base clock (internal signal) xcki input from xckn pin (internal signal). used for synchronous slave operation xcko clock output to xckn (internal signal). used for synchronous master operation f osc xtal pin frequency (system clock) the usart supports the followi ng four clock operating modes: normal asynchronous mode double-speed asynchronous mode master synchronous mode slave synchronous mode the umseln bit selects between asynchronous and synchronous operation. in asynchronous mo de, the speed is controlled by the u2x bit. in synchronous mode, the direction bit of the xckn pin (ddr_x ckn) in the data direction regi ster, where the xckn pin is located (ddrx), controls whether the clock source is internal (master mode) or external (slave mode). the xckn pin is active in synchronous mode only. 17.4.1 internal clock generation ? the baud rate generator internal clock generation is used for the asynchronous and th e synchronous master operating mode s. the description in this section refers to figure 17-2 on page 139 . the usart baud rate register (ubrrn) a nd the down-counter connected to it function as a programmable prescaler, or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to ?0? or when ubrrnl is written. a clock is generated each time the counter reaches ?0?. this is the baud rate generat or clock output and has a frequency of f osc /(ubrrn+1). depending on the operating mode, the transmitter di vides the baud rate generator clock output by 2, 8, or 16. the baud rate generator output is used directly by the receiver?s clock and dat a recovery units. however, the recovery units use a state machine that uses 2, 8, or 16 states, depending on the mode set by umseln, u2xn, and ddr_xckn bits. sync register edge detector prescaling down-counter /2 xck pin /4 0 0 1 1 0 1 0 1 /2 ubrr ddr_xck ucpol u2x ddr_xck ubrr+1 txclk rxclk umsel fosc osc xcki xcko attiny1634 [preliminary datasheet] 9296c?avr?07/14 140 table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculating the ubrrn value for each operating mode using an internally generated clock source. note: 1. the baud rate is defined as the transfer rate in bits per second (bps). signal description for table 17-1 : baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrr contents of the ubrrhn and ubrrln registers, (0-4095) some examples of ubrrn values for selected system clock frequencies are shown in section 17.11 ?examples of baud rate setting? on page 154 . 17.4.2 double-speed operation the transfer rate can be doubled by setting the u2xn bit. setting this bit only has an effect in asynchronous operating mode. in synchronous operating mode this bit should be cleared. setting this bit reduces the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note, however, that in this case th e receiver only uses half the number of samples. in double- speed mode, the number of data and clock re covery samples are reduced from 16 to 8, and therefore a more accurate baud rate setting and system clock are required. there are no downsides for the transmitter. 17.4.3 external clock external clocking is used in synchronous slave operating modes. to minimize the chance of meta-stability, the external clock input from the xck pin is sampled by a synchronization regist er. the output from the synchr onization register then passes through an edge detector before it is used by the transmit ter and receiver. this process introduces a delay of two cpu clocks and the maximum external clock frequen cy is thus limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefore recommended to add some margin to avoid possible data loss due to frequency variations. table 17-1. equations for calculat ing baud rate register setting operating mode baud rate (1) ubrr value asynchronous normal mode (u2xn = 0) asynchronous double-speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrrn 1 + () --------------------------------------- = ubrrn f osc 16baud ---------------------- - 1 ? = baud f osc 8 ubrrn 1 + () ------------------------------------ = ubrrn f osc 8baud ------------------- - 1 ? = baud f osc 2 ubrrn 1 + () ------------------------------------ = ubrrn f osc 2baud ------------------- - 1 ? = f xckn f osc 4 ---------- - < 141 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.4.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin is used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edg e of the edge where the data output (txdn) is changed. figure 17-3. synchronous mode xckn timing the ucpoln bit ucrsc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 17-3 shows, when ucpoln is ?0?, the dat a is changed at the rising xckn edge and sampled at the falling xckn edge. if ucpoln is set, the data is changed at the falling xckn edge and sampled at the rising xckn edge. 17.5 frame formats a serial frame is defined as one characte r of data bits with synchroniza tion bits (start and stop bits), and optionally a parit y bit for error checking. the usart accepts all 30 combin ations of the following as valid frame formats: start bit: 1 data bits: 5, 6, 7, 8, or 9 parity bit: no, even, or odd parity stop bits: 1, or 2 a frame begins with the start bit followed by the least significan t data bit. the other data bits then follow, the last one bei ng the most significant bit. if enabled, the parity bit is inserted after the data bits before the stop bits. when a complete fram e has been transmitted, it can be followed directly by a new fram e or the communication line can be set to an idle (high) state. figure 17-4 illustrates the possible combinations of the fr ame formats. bits inside brackets are optional. figure 17-4. frame formats signal description for figure 17-4 : st start bit (always low) (n) data bits (0 to 4/5/6/7/8) p parity bit if enabled (odd or even) sp stop bit (always high) idle no transfers on the communication line (rxdn or txdn) (high) xck rxd/txd xck ucpol = 1 ucpol = 0 rxd/txd sample sample st 0 1 2 3 4 [5] [6] [7] [8] (st/idle) (idle) frame [p] sp1 [sp2] attiny1634 [preliminary datasheet] 9296c?avr?07/14 142 the frame format used by the usart is set by the ucszn, upmn, and usbsn bits as follows: the usart character size bits (ucszn) select the number of data bits in the frame the usart parity mode bits (upmn) choose the type of parity bit the selection between one or two stop bits is done by the usart stop bit select bit (usbsn). the receiver ignores the second stop bit. a frame error (fe) is therefore only detected in ca ses where the first stop bit is ?0?. the receiver and transmitter use the same setting. note that changing the setting of any of t hese bits corrupts all ongoing communication for both the receiver and transmitter. 17.5.1 parity bit calculation the parity bit is calculated by doing an ?exclusive or? of all the data bits. if odd parity is us ed, the result of the ?exclusi ve or? is inverted. the relation between the parity bit and data bits is as follows: p even = d n ? 1 ... d 3 d 2 d 1 d 0 0 p odd = d n ? 1 ... d 3 d 2 d 1 d 0 1 ... where: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and the first stop bit of a serial frame. 17.6 usart initialization the usart has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting frame format and, depending on th e method of use, enabling the transmitter or the receiver. for interrupt driven usart operation, the global interrupt flag should be cleared and the usart interrupts disabled. before re-initializing baud rate or frame format, it should be checked that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the tran smitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buf fer. note that, if used, the txcn flag must be cleared before each transmission (before udrn is written). the following simple usart initialization code examples sh ow one assembly and one c function that are equal in functionality. the examples assume asyn chronous operation using polling (no interr upts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 143 attiny1634 [preliminary datasheet] 9296c?avr?07/14 note: 1. see section 4.2 ?code examples? on page 7 . more advanced initialization routines can be done that include frame format as parame ters, disable interrupts, etc. however, many applications use a fixed setting of th e baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine or be combined with initialization code for other i/o modules. 17.7 data transmission ? the usart transmitter the usart transmitter is enabled by setting the transmit enabl e bit (txenn). when the transmitter is enabled, the normal port operation of the txdn pin is overridden by the usart and given the transmitter?s serial output function. the baud rate, operating mode, and frame format must be set up once befor e doing any transmissions. if synchronous operation is used, the clock on the xckn pin is overridden and used as the transmission clock. 17.7.1 sending frames with 5 to 8 data bits a data transmission is initiated by loading the transmit buffer with the data to be transmitted. the cpu can load the transmit buffer by writing to the udrn register. the buffered data in the transmit buffer is moved to the shift register when it is read y to send a new frame. the shift register is loaded with new data if it is in idle state (no ong oing transmission), or immediatel y after the last stop bit of the pr evious frame is transmitted. when the shift regist er is loaded with new data, it transfers one complete frame at the rate given by the baud rate register, the u2xn bit, or by xckn, depending on the operating mode. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< attiny1634 [preliminary datasheet] 9296c?avr?07/14 148 17.8.3 receive compete flag and interrupt the usart receiver has one flag th at indicates the receiver state. the receive complete flag (rxcn) indicates if there are unrea d data present in the receive buf fer. this flag is set when unread data exist in the receive buffer. the flag is cleared when the receive buffer is empty (i.e., it does not contain any unread data). if the receiver is disabled (rxenn = 0), the rece ive buffer is flushed, causing the rxcn bit to become ?0?. when the receive complete interrupt enable (rxcien) is set, the usart receive complete interrupt is executed as long as the rxcn flag is set (provided that global interrupts are enabled ). when interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in or der to clear the rxcn flag. ot herwise, a new interrupt occurs once the interrupt routine terminates. 17.8.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn), and parity error (upen). all can be accessed by reading ucsrna. the error flags are commonly loca ted in the receive buffer together with the frame for which they indicate the error status. due to t he buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), because reading the udrn i/o location changes the buffer r ead location. another attribute of error flags is that they cannot be altered by software writing to the flag location. however, to ensure upward compatibility of future usart implementations, all flags must be set to ?0? when the ucsrna is written. none of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame st ored in the receive buffer. t he fen flag is ?0? when the stop bit was re ad correctly (as ?1?) and the fen flag is ?1 ? when the stop bit was incorrect (?0?). th is flag can be used for detecting out-of-sync co nditions, break conditions, and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrn c because the receiver ignor es all stop bits except for the first stop bits. for compatibility with future devices, always set this bit to ?0? when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a re ceiver buffer full condition. a data overrun occurs when the receive buffer is full (two characters), a new character is waiting in the receive shift register, or a new start bit is detect ed. if the dorn flag is set, there was one or more serial frame lost between the frame last re ad from udrn and the next frame read from udrn. for compatibility with future devices, always write this bit to ?0? wh en writing to ucsrna. the dorn flag is cleared when the frame received was successfully move d from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled, the upen bit always reads as ?0?. for comp atibility with future devices, always set this bit to ?0? when writing to ucsrna. for more information, see section 17.5.1 ?parity bit calculation? on page 142 and section 17.8.5 ?parity checker? on page 148 . 17.8.5 parity checker the parity checker is active when the high usart parity mode bit (upmn1) is set. the type of parity check to be performed (odd or even) is selected by the upmn0 bit. when enabled, t he parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error flag (upen) can then be read by software to check if the frame had a parity error. if parity checking is enabled, the upen bit is set if the next ch aracter that can be read from the receive buffer had a parity error when received. this bit is valid until the receive buffer (udrn) is read. 17.8.6 disabling the receiver unlike the transmitter, the receiver is disabled immediatel y and any data from ongoing receptions is lost. when disabled (rxenn = 0), the receiver no longer overrides the normal functi on of the rxdn port pin and the fifo buffer is flushed with any remaining data in the buffer lost. 149 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.8.7 flushing the receive buffer the receiver buffer fifo is flushed when the receiver is disabl ed, i.e., the buffer is emptied of its contents. unread data is lost. to flush the buffer during normal oper ation, for example, due to an error condition, read the udrn until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see section 4.2 ?code examples? on page 7 . 17.9 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic samples and low-pass filters each incoming bit, improv ing the noise immunity of the receiver. the operational range of asynchronous reception depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the fr ame size in number of bits. 17.9.1 asynchronous clock recovery the clock recovery logic synchro nizes the internal clock to the incoming serial frames. figure 17-5 illustrates the sampling process of the start bit of an incoming frame. in normal mode the sample rate is 16 times the baud rate, in double-speed mode eight times. the horizontal arrows illustrate the synchroniza tion variation due to the samp ling process. note the larger time variation when using the double-speed operating mode (u2xn = 1). samples denoted ?0? are samples done when the rxdn line is idle (i.e., no communication activity). figure 17-5. start bit sampling when the clock recovery logic detects a high (idle) to low (sta rt) transition on the rxdn line, the start bit detection sequenc e is initiated. in figure 17-5 samples are indicated with numbers inside boxes and sample number 1 denotes the first ?0? sample. the clock recovery logic then uses samples 8, 9, and 10 (in normal mode), or samples 4, 5, and 6 (in double-speed mode) to decide if a valid start bit is rece ived. if two or more of these three sample s have logic high levels (the majority wi ns), the start bit is rejected as a noise spike and the receiver star ts looking for the next high-to-low transition. if, however, a valid start bit is detected, the cloc k recovery logic is synchronized and the data re covery can begin. the synchronization process is repeated for each start bit. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while (ucsrna & (1< 151 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.9.3 asynchronous operational range the operational range of the receiver depends on the mismatch between the receiv ed bit rate and the internally generated baud rate. if the transmitter is sending frames excessively fast or slow bit rates, or the internally generated baud rate of th e receiver does not have a similar base frequency (see table 17-2 on page 151 ), the receiver is not able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ... where: d sum of character size and parity size (d = 5 to 10 bit) s samples per bit, 16 for normal speed mode, or 8 for double-speed mode s f first sample number used for majority voting, 8 (normal speed), or 4 (double) s m middle sample number for majority voting, 9 (normal speed), or 5 (double speed) r slow the ratio of the slowest incoming data rate that can be accepted with respect to the receiver baud rate r fast the ratio of the fastest incoming data rate that ca n be accepted with respect to the receiver baud rate table 17-2 and table 17-3 list the maximum receiver baud rate error that c an be tolerated. note t hat normal speed mode has higher toleration of baud rate variations. the recommendations of the maximum receiver baud rate error are made under the assumption that the receiver and transmitter divide the maximum total error equally. there are two possible sources for the receiver baud rate error: the system clock of the receiver always has some minor instability over the supply voltage range and the temperature range. the second source for error is more controllable. the baud rate generator cannot always do an exact division of the system frequency to get the desired baud rate. in this case, an ubrr value th at produces an acceptable low error should be used if possible. table 17-2. recommended maximum receiver baud rate error in normal speed mode d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/?6.8 3.0 6 94.12 105.79 +5.79/?5.88 2.5 7 94.81 105.11 +5.11/?5.19 2.0 8 95.36 104.58 +4.58/?4.54 2.0 9 95.81 104.14 +4.14/?4.19 1.5 10 96.17 103.78 +3.78/?3.83 1.5 table 17-3. recommended maximum receiver baud rate error in double-speed mode d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/?5.88 2.5 6 94.92 104.92 +4.92/?5.08 2.0 7 95.52 104,35 +4.35/?4.48 1.5 8 96.00 103.90 +3.90/?4.00 1.5 9 96.39 103.53 +3.53/?3.61 1.5 10 96.70 103.23 +3.23/?3.30 1.0 r slow d1 + () s s1 ? dss f + + -------------------------------------------- - = r fast d2 + () s d1 + () ss m + ----------------------------------- - = attiny1634 [preliminary datasheet] 9296c?avr?07/14 152 17.9.4 start frame detection the usart start frame detector can wake up the mcu from power-down, standby, or adc noise reduction sleep mode when it detects a start bit. when a high-to-low transition is detected on rxdn, the intern al 8mhz oscillator is powered up and the usart clock is enabled. after start-up, the rest of the data frame can be received, provided t hat the baud rate is slow enough in relation to the internal 8mhz oscillator start-up time . start-up time of the internal 8mhz o scillator varies with supply voltage and temperature. the usart start frame detection works both in asynchronous an d synchronous modes. it is enabled by writing the start frame detection enable bit (sfden). if the usart start interrupt enable (rxsie) bit is set, the usart receive start interrupt is generated immediately when start is detected. when using the feature without start interr upt, the start detection logic activates the internal 8mhz oscillator and the usart clock only while the frame is being received. other clocks rema in stopped until the receive co mplete interrupt wakes up the mcu. the maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from as specified here: idle or adc noise reduction sleep mode: system clock frequency divided by four standby or power-down: 500kb/s the maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up from as specified here: idle sleep mode: the same as in active mode. other sleep modes: see table 17-4 and table 17-5 . table 17-4. maximum total baud rate error in normal speed mode baud rate frame size 5 6 7 8 9 10 0 to 28.8kb/s +6.67 ?5.88 +5.79 ?5.08 +5.11 ?4.48 +4.58 ?4.00 +4.14 ?3.61 +3.78 ?3.30 38.4kb/s +6.63 ?5.88 +5.75 ?5.08 +5.08 ?4.48 +4.55 ?4.00 +4.12 ?3.61 +3.76 ?3.30 57.6kb/s +6.10 ?5.88 +5.30 ?-5.08 +4.69 ?4.48 +4.20 ?4.00 +3.80 ?3.61 +3.47 ?3.30 76.8kb/s +5.59 ?5.88 +4.85 ?5.08 +4.29 ?4.48 +3.85 ?4.00 +3.48 ?3.61 +3.18 ?3.30 115.2kb/s +4.57 ?5.88 +3.97 ?5.08 +3.51 ?4.48 +3.15 ?4.00 +2.86 ?3.61 +2.61 ?3.30 table 17-5. maximum total baud rate error in double-speed mode baud rate frame size 5 6 7 8 9 10 0 to 57.6kb/s +5.66 ?4.00 +4.92 ?3.45 +4.35 ?3.03 +3.90 ?2.70 +3.53 ?2.44 +3.23 ?2.22 76.8kb/s +5.59 ?4.00 +4.85 ?3.45 +4.29 ?3.03 +3.85 ?2.70 +3.48 ?2.44 +3.18 ?2.22 115.2kb/s +4.57 ?4.00 +3.97 ?3.45 +3.51 ?3.03 +3.15 ?2.70 +2.86 ?2.44 +2.61 ?2.22 153 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.10 multiprocessor communication mode setting the multiprocessor communication mode bit (mpcmn) enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information ar e ignored and not put into t he receive buffer. in a system with multiple mcus that communicate via the same serial bus this effectiv ely reduces the number of incoming frames that has to be handled by the cpu. the transmitte r is unaffected by the mpcmn bit, but has to be used differently when it is a part of a system utilizing the mult iprocessor communication mode. if the receiver is set up to receive fram es that contain 5 to 8 data bits, then the first stop bit indicates if the frame conta ins data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the fi rst stop or the ninth bit) is ?1?, the frame contains an address. when the frame type bit is ?0?, the frame is a data frame. the multiprocessor communication mode enables several slave mcus to receive data from a mast er mcu. this is done by first decoding an address frame to find out which mcu has be en addressed. if a particular slave mcu has been addressed, it receives the following data frames as normal whereas th e other slave mcus ignore the received frames until another address frame is received. for an mcu to act as a master mcu, it can use a 9-bit char acter frame format. the ninth bit (txb8) must be set when an address frame is transmitted and cleared when a data frame is tr ansmitted. in this case, the slave mcus must be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multiprocessor communication mode: 1. all slave mcus are set to multipro cessor communication mode (mpcmn = 1). 2. the master mcu sends an address frame and all slaves receive and read this frame. in the slave mcus the rxcn flag is set as normal. 3. each slave mcu reads udrn and determines if it has been sele cted. if so, it clears the mpcmn bit. if not, it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu receives all data frames until a new address frame is received. the other slave mcus, which still have the mpcmn bit set, ignore the data frames. 5. when the last data frame is received by the addre ssed mcu, it sets the mpcmn bit and waits for a new address frame from master. the process then repeats from step 2. though possible, it is impractical to use any of the 5- to 8-bit charac ter frame formats due to the fact that the receiver woul d then have to alternate between using n and n+1 character frame formats. this makes full-duplex operation difficult because the transmitter and receiver use the same character size setting. if 5- to 8-bit character frames are used, the transmitter mus t be set to use two stop bits as the first stop bit is used for indicating the frame type. do not use read-modify-write instructions (sbi and cbi) to se t or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidental ly be cleared when using sbi or cbi instructions. attiny1634 [preliminary datasheet] 9296c?avr?07/14 154 17.11 examples of baud rate setting commonly used baud rates for asynchronous operatio n can be generated by usin g the ubrr settings in section 17.11 ?examples of baud rate setting? on page 154 . ubrr values which yield an actual ba ud rate differing less than 0.5% from the target baud rate are shown in bold. higher error ratings ar e acceptable, but the receiver has less noise resistance when the error ratings are high?especially for large serial frames (see section 17.9.3 ?asynchronous operational range? on page 151 ). the error values are calcul ated using the following equation: error[%] baudrate closest match baudrate -------------------------------------------------- 1 ? ?? ?? 100% = table 17-6. examples of ubrr settings for commonly used oscillator frequencies baud rate (bps) f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 ?7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 ?3.5% 7 0.0% 15 0.0% 8 ?3.5% 16 2.1% 19.2k 2 8.5% 6 ?7.0% 5 0.0% 11 0.0% 6 ?7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 ?3.5% 38.4k 1 ?18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 ?7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 ?18.6% 1 ?25.0% 2 0.0% 1 ?18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k ? ? ? ? ? ? 0 0.0% ? ? ? ? 250k ? ? ? ? ? ? ? ? ? ? 0 0.0% max. (1) 62.5kb/s 125kb/s 115.2kb/s 230.4kb/s 125kb/s 250kb/s note: 1. ubrr = 0, error = 0.0% 155 attiny1634 [preliminary datasheet] 9296c?avr?07/14 table 17-7. examples of ubrr setti ngs for commonly used oscilla tor frequencies (continued) baud rate (bps) f osc = 3.6864mhz f osc = 1.0000mhz f osc = 7.3728mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 ?0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 ?3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 ?7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 ?3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 ?7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 ?7.8% 1 ?7.8% 0 0.0% 1 0.0% 1 ?7.8% 3 ?7.8% 0.5m ? ? 0 ?7.8% ? ? 0 0.0% 0 ?7.8% 1 ?7.8% 1m ? ? ? ? ? ? ? ? ? ? 0 ?7.8% max. (1) 230.4kb/s 460.8kb/s 250kb/s 0.5mb/s 460.8kb/s 921.6kb/s note: 1. ubrr = 0, error = 0.0% table 17-8. examples of ubrr setti ngs for commonly used oscilla tor frequencies (continued) baud rate (bps) f osc = 8.0000mhz f osc = 11.0592mhz f osc = 14.7456mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 207 0.2% 416 ?0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 ?0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 ?0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 ?3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 ?7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 ?3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 ?7.8% 5 ?7.8% 3 ?7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 ?7.8% 1 ?7.8% 3 ?7.8% 1m ? ? 0 0.0% ? ? ? ? 0 ?7.8% 1 ?7.8% max. (1) 0.5mb/s 1mb/s 691.2kb/s 1.3824mb/s 921.6kb/s 1.8432mb/s note: 1. ubrr = 0, error = 0.0% attiny1634 [preliminary datasheet] 9296c?avr?07/14 156 17.12 register description 17.12.1 udrn ? usart i/o data register the usart transmit data buffer and usart receive data buff er registers share the same i/o address, referred to as usart data register or udrn. data written to udrn goes to the transmit data buffer register (txb). reading udr returns the contents of the receive data buffer register (rxb). for 5-, 6-, or 7-bit characters, the upper unused bits are i gnored by the transmitter and set to ?0? by the receiver. the transmit buffer can only be written wh en the udren flag is set. data written to udrn when the udren flag is not set is ignored. when the transmitter is enabled and data is written to the transmit buffer, the trans mitter loads the data into the transmit shift register when it is empty. the da ta is then serially transmitted on the txdn pin. the receive buffer consists of a two-leve l fifo. the fifo changes its state whenever the receive bu ffer is accessed. due to this behavior of the receive buffer, read-modify-write instructions (sbi and cbi) should not be used to access this location. care should also be taken when using bit test instructions (sbic and sbis) because these also change the state of the fifo. table 17-9. examples of ubrr setti ngs for commonly used oscilla tor frequencies (continued) baud rate (bps) f osc = 16.0000mhz f osc = 18.4320mhz f osc = 20.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 416 ?0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 ?0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 ?0.1% 79 0.0% 159 0.0% 86 ?0.2% 173 ?0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 ?0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 ?0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 ?1.4% 64 0.2% 57.6k 16 2.1% 34 ?0.8% 19 0.0% 39 0.0% 21 ?1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 ?1.4% 115.2k 8 ?3.5% 16 2.1% 9 0.0% 19 0.0% 10 ?1.4% 21 ?1.4% 230.4k 3 8.5% 8 ?3.5% 4 0.0% 9 0.0% 4 8.5% 10 ?1.4% 250k 3 0.0% 7 0.0% 4 ?7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 0 0.0% 1 0.0% ? ? ? ? ? ? ? ? max. (1) 1mbps 2mbps 1.152mbps 2.304mbps 1.25mbps 2.5mb/s note: 1. ubrr = 0, error = 0.0% bit 76543210 0x20 (0x40) rxb[7:0] udr0 (read) 0x20 (0x40) txb[7:0] udr0 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x73) rxb[7:0] udr1 (read) (0x73) txb[7:0] udr1 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 157 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.12.2 ucsrna ? usart control and status register a bit 7 ? rxcn: usart receive complete this flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer is flushed causing the rxcn flag to become ?0?. the flag can be used to generate a receive complete interrupt (see rxcien bit). bit 6 ? txcn: usart transmit complete this flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer (udrn). th e txcn flag bit is automatically cleared when a transmit complete interrupt is executed or it can be cleared by writing a ?1? to its bit location. the flag c an generate a transmit complete interrupt (see txcien bit). bit 5 ? udren: usart data register empty this flag indicates that the transmit buffer (udrn) is ready to receive new data. if udren is ?1?, the buffer is empty and therefore ready to be written to. th e udren flag can generate a data register empty interrupt (see udrien bit). the udren flag is set after a reset to in dicate that the transmitter is ready. bit 4 ? fen: frame error this flag is set if the next character in the receive buffer had a frame error when received (i.e., when the first stop bit of the next character in the receive buffer is ?0?). this bit is vali d until the receive buffer (udrn) is read. the fen bit is ?0? whe n the stop bit of received data is ?1?. always set this bit to ?0? when writing the register. bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when th e receive buffer is full (two characters) , a new character is waiting in the receive shift register, or a ne w start bit is detected. this bit is valid until the receive buf fer (udrn) is read. always set this bit to ?0? when writing the register. bit 2 ? upen: usart parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enable d at that point (upmn1 = 1). this bit is va lid until the receive bu ffer (udrn) is read. always set this bit to ?0? when writing the register. bit 1 ? u2xn: double the usart transmission speed this bit only has effect for asynchronous operation. write this bit to ?0? when using synchronous operation. writing this bit to ?1? reduces the divisor of the baud rate di vider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. bit 76543210 0x26 (0x46) rxc0 txc0n udre0n fe0 dor0 upe0 u2x0 mpcm0 ucsr0a read/write r r/w rrrrr/wr/w initial value00100000 bit 76543210 (0x79) rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 ucsr1a read/write r r/w rrrrr/wr/w initial value00100000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 158 bit 0 ? mpcmn: multiprocessor communication mode this bit enables multiprocessor communication mode. when the bit is written to ?1?, all the inco ming frames received by the usart receiver that do not contain address information are igno red. the transmitter is unaffe cted by the mpcmn bit. for more information, see section 17.10 ?multiprocessor communication mode? on page 153 . 17.12.3 ucsrnb ? usart control and status register b bit 7 ? rxcien: rx complete interrupt enable writing this bit to ?1? enables interrupt on the rxcn flag. a usart receive complete interrupt is generated only if the rxci en bit, the global interrupt flag, and the rxcn bits are set. bit 6 ? txcien: tx complete interrupt enable writing this bit to ?1? enables interrupt on the txcn flag. a usart receive complete interrupt is generated only if the txcien bit, the global interrupt flag, and the txcn bits are set. bit 5 ? udrien: usart data regi ster empty interrupt enable writing this bit to ?1? enables interrupt on the udren flag. a data register empty interrupt is generated only if the udrien bit is written to ?1?, the global interrupt flag in sreg is wri tten to ?1?, and the udren bit in ucsrna is set. bit 4 ? rxenn: receiver enable writing this bit to ?1? enables the usart receiver. when enable d, the receiver overrides normal port operation for the rxdn pin. writing this bit to ?0? disables the receiver. disabling the rece iver flushes the receive buffer, invalidating the fen, dorn, a nd upen flags. bit 3 ? txenn: transmitter enable writing this bit to ?0? enables the usart transmitter. when enabled, the transmitter overrides normal port operation for the txdn pin. writing this bit to ?0? disables the transmitter. disabling the transmitter becomes effective after ongoing and pending transmissions are completed, i.e., when the transmit shift regi ster and transmit buffer register do not contain data to be transmitted. when disabled, the transmitter no longer overrides the txdn port. bit 2 ? ucszn2: character size the ucszn2 bit combined with the ucszn[1:0] bits set the number of data bits (character size) in the frame the receiver and transmitter use. bit 1 ? rxb8n: receive data bit 8 rxb8n is the ninth data bit of the received character when opera ting with serial frames with nine data bits. it must be read before reading the low bits from udrn. bit 76543210 0x25 (0x45) rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 ucsr0b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 bit 76543210 (0x78) rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 ucsr1b read/write r/w r/w r/w r/w r/w r/w r r/w initial value00000000 159 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 0 ? txb8n: transmit data bit 8 txb8n is the ninth data bit in the character to be transmitted w hen operating with serial frames with nine data bits. it must b e written before writing the low bits to udrn. 17.12.4 ucsrnc ? usart control and status register c bits 7:6 ? umseln[1:0]: usart mode select these bits select the operating mode of the usart as shown in table 17-10 . note: 1. for a complete description of master spi mode (mspim) operation, see section 18. ?usart in spi mode? on page 162 . bits 5:4 ? upmn1:0: parity mode these bits enable and set the type of parity generation and check. if enabled, the transmitter automatically generates and sends the parity of the transmitted data bits within each frame. the receiver generat es a parity value for the incoming data and compares it to the upmn setting. if a mismatch is detected, the upen flag is set. bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. bit 7 6 543210 0x24 (0x44) umsel01 umsel00 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 ucsr0c read/write r r/w r/w r/w r/w r/w r/w r/w initial value0 0 000110 bit 7 6 543210 (0x77) umsel11 umsel10 upm11 upm10 usb s1 ucsz11 ucsz10 ucpol1 ucsr1c read/write r r/w r/w r/w r/w r/w r/w r/w initial value0 0 000110 table 17-10. umseln bit settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 reserved 1 1 master spi (mspim) (1) table 17-11. parity mode selection upmn1 upmn0 parity mode 0 0 disabled 0 1 reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 17-12. usbsn bit settings usbsn stop bit(s) 0 1-bit 1 2-bit attiny1634 [preliminary datasheet] 9296c?avr?07/14 160 bits 2:1 ? ucszn[1:0]: character size the ucszn[1:0] bits combined with the ucszn2 bit in ucsrnb set the number of data bits (c haracter size) in a frame the receiver and transmitter use (see table 17-13 ). bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to ?0? when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and dat a input sample and the synchronous clock (xckn). 17.12.5 ucsrnd ? usart control and status register d bit 7 ? rxsien: usart rx start interrupt enable writing this bit to ?1? enables the interrupt on the rxsn flag. in sleep modes this bit enables the start frame detector that c an wake up the mcu when a start condition is detected on the rxdn line. the usart rx start interrupt is genera ted only if the rxsien bit, the global interrupt enable flag, and rxsn are set. bit 6 ? rxsn: usart rx start this flag is set when a start condition is detected on the rxdn line. if the rxsien bit and the global interrupt enable flag ar e set, an rx start interrupt is generated when this flag is set. the flag can only be cleared by writing a logic one to the rxsn bit location. if the start frame detector is enabled and the global interrupt enable flag is set, t he rx start interrupt wakes up the mcu fro m all sleep modes. table 17-13. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 9-bit table 17-14. clock polarity settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge bit 76543210 0x23 (0x43) rxsie0 rxs0 sfde0 ? ? ? ? ? ucsr0d read/write r/w r/w rrrrrr initial value00100000 bit 76543210 (0x76) rxsie1 rxs1 sfde1 ? ? ? ? ? ucsr1d read/write r/w r/w rrrrrr initial value00100000 161 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 5 ? sfden: start frame detection enable writing this bit to ?1? enables the usart start frame detectio n mode. the start frame detector is able to wake up the mcu from sleep mode when a start condition, i.e., a high (idle) to low (start) transition, is detected on the rxdn line. for more information, see section 17.9.4 ?start frame detection? on page 152 . bits 4:0 ? res: reserved bits these bits are reserved bits in the atmel ? attiny1634 and are always read as ?0?. 17.12.6 ubrrnl and ubrrnh ? usart baud rate registers bits 15:12 ? res: reserved bits these bits are reserved for future use. for compatibility with future devices, these bits must be written to ?0? when ubrrnh is written. bits 11:0 ? ubrr[11:0]: usart baud rate register this is a 12-bit register which contai ns the usart baud rate. ubrrnh contains the four most significant bits and ubrrnl contains the eight least significant bits of the usart baud rate. writing to ubrrnl triggers an immediate u pdate of the baud rate prescaler. ongo ing transmissions by the transmitter and receiver are corrupted when the baud rate is changed. table 17-15. usart start frame detection modes sfden rxsien rxcien description 0 x x start frame detector disabled 1 0 0 reserved 1 0 1 start frame detector enabled. the rxcn flag wakes up mcu from all sleep modes. 1 1 0 start frame detector enabled. the rxsn flag wakes up mcu from all sleep modes. 1 1 1 start frame detector enabled. both rxcn and rxsn wake up the mcu from all sleep modes. initial value 0 0 0 0 0 0 0 0 read/write r r r r r/w r/w r/w r/w bit 151413121110 9 8 0x22 (0x42) ? ? ? ? ubrr0[11:8] ubrr0h 0x21 (0x41) ubrr0[7:0] ubrr0l bit 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r/w r/w r/w r/w bit 151413121110 9 8 (0x75) ? ? ? ? ubrr1[11:8] ubrr1h (0x74) ubrr1[7:0] ubrr1l bit 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 162 18. usart in spi mode 18.1 features full duplex, three-wire synchronous data transfer master operation supports all four spi operating modes (mode 0, 1, 2, and 3) lsb first or msb first data transfer (configurable data order) queued operation (double-buffered) high-resolution baud rate generator high-speed operation (fxckmax = fck/2) flexible interrupt generation 18.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) can be set to an operating mode compliant with master spi. setting both umseln[1:0] bits to ?1? enables the usart in m spim logic. in this operating mo de the spi master control logic takes direct control of the usart resources. these resources include the transmitter and receiv er shift registers and buffers and the baud rate generator. the parity gene rator and checker, the data and clock reco very logic, and the rx and tx control logic are disabled. the usart rx and tx control logic is replac ed by a common spi transfer control logic. however, the pin control logic and interrupt generation logic is identical in both operating modes. the i/o register locations are the same in both modes. however, some of the functionality of the control registers changes when using mspim. 18.3 clock generation the clock generation logic generates the base clock for th e transmitter and receiver. for the usart mspim operating mode, only internal clock generation (i.e., master operation) is supported. therefore, for the usart in mspim to operate correctly, the data direction register ( ddrx) where the xck pin is located must be configured to set the pin as output (ddr_xckn = 1). it is advisable to set up the ddr_xckn bef ore the usart in mspim is enabled (i.e., before txenn and rxenn bits are set). the internal clock generation used in mspim mode is identica l to the usart synchronous master mode. the baud rate or ubrr setting can therefore be calcul ated using the same equations (see table 18-1 ). note: 1. the baud rate is defined as the transfer rate in bits per second (bps). baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of ubrrnh and ubrrnl, (0-4095) table 18-1. equations for calculat ing baud rate register setting operating mode calculating baud rate (1) calculating ubrr value synchronous master mode baud f osc 2 ubrrn 1 + () ------------------------------------ = ubrrn f osc 2baud ------------------- - 1 ? = 163 attiny1634 [preliminary datasheet] 9296c?avr?07/14 18.4 spi data modes and timing with respect to serial data, there are four combinations of xckn (sck) phase and polarit y which are determined by the ucphan and ucpoln control bits. the data tr ansfer timing diagrams are shown in figure 18-1 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring sufficient time for data signals to stabilize. the ucpoln and ucphan functionality is summarized in table 18-2 . note that changing the setting of any of these bits corrupts all ongoing communication for both the receiver and transmitter. figure 18-1. ucphan and ucpoln data transfer timing diagrams 18.5 frame formats a serial frame for the mspim is defined as one character of eight data bits. the usart in mspim mode has two valid frame formats: 8-bit data with msb first 8-bit data with lsb first a frame starts with the least or most significant data bit. afte r this follows the next data bits up to a total of eight, endin g with the most or least significant bit. when a complete frame is transmitted, a new frame can follow it directly or the communication line can be set to an idle (high) state. the udordn bit sets the frame format used by the usart in mspim mode. the receiver and transmitter use the same setting. note that changing the setting of any of these bits corrupts all ongoing communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writ ing two data bytes to udrn. a usart transmit complete interrupt then signals that the 16-bit value has been shifted out. table 18-2. ucpoln and ucphan functionality ucpoln ucphan spi mode leading edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck ucpol = 0 ucpol = 1 ucpha = 1 ucpha = 0 data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) attiny1634 [preliminary datasheet] 9296c?avr?07/14 164 18.5.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting the ma ster operating mode, setting the frame format, and enabling the transmitter and receiver. only the transm itter can operate independently. for interru pt-driven usart operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: the baud-rate register (ubrrn) must be ?0? when the transmitter is enabled to ensure immediate initialization of the xckn output. unlike the norma l usart operating mode, the ubrrn mu st then be written to the desired value after the transmitter is enabled but before the fi rst transmission is started. setting ubrrn to ?0? before enabling the transmitter is not necessary if the initia lization is done immediately after a reset because ubrrn is reset to ?0?. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there are no ongoing transmissions during the period the regist ers are changed. the txcn flag can be us ed to check that the transmitter has completed all transfers, and the rxcn flag can be used to che ck that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples sh ow one assembly and one c function that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is a ssumed to be stored in registers r17:r16. note: 1. see section 4.2 ?code examples? on page 7 . assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; setmspi mode of operation and spi data mode 0. ldi r18, (1< 167 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 7 ? rxcn: usart receive complete this flag is set when there is unread data in the receive bu ffer. the flag is cleared when t he receive buffer is empty (i.e., does not contain any unread data). if the rece iver is disabled, the receive buffer is flushed, causing the flag to become ?0?. the flag can be used to generate a receive complete interrupt (see rxcien bit). bit 6 ? txcn: usart transmit complete this flag is set when the entire frame in the transmit shif t register has been shifted out and there is no new data in the transmit buffer (udrn). the flag is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a ?1? to its bit location. this flag can generate a transmit complete interrupt (see txcien bit). bit 5 ? udren: usart data register empty this flag indicates the transmit buffer (udrn) is ready to rece ive new data. if the flag is ?1?, the buffer is empty and ready to be written. the flag is set after a reset to indicate that th e transmitter is ready. the flag can generate a data register empty interrupt (see udrien bit). bits 4:0 ? reserved bits in mspi mode in mspi mode these bits are reserved for future use. for com patibility with future devices, thes e bits must be written as ?0?. 18.8.3 ucsrnb ? usartmspim control and status register n b bit 7 ? rxcien: rx complete interrupt enable writing this bit to ?1? enables interrupt on the rxcn flag. a usart receive complete interrupt will be generated only if the rxcien bit is written to ?1?, the global interrupt flag in sreg is written to ?1?, and the rxcn bit is set. bit 6 ? txcien: tx complete interrupt enable writing this bit to ?1? enables interrupt on the txcn flag. a usart transmit complete interrupt will be generated only if the txcien bit is written to ?1?, the global interrupt flag in sreg is written to ?1?, and the txcn bit is set. bit 5 ? udrie: usart data regi ster empty interrupt enable writing this bit to ?1? enables interrupt on the udren flag. a data register empty interrupt is generated only if the udrien bi t is written to ?1?, the global interrupt flag in sreg is written to ?1?, and the udren bit is set. bit 4 ? rxenn: receiver enable writing this bit to ?1? enables the usart receiver in m spim mode. when enabled, the receiver overrides normal port operation for the rxdn pin. disabling the receiver flushes the receive buffer. enabling the receiver only and leaving t he transmitter disabled has no meaning in mspi mode, because only master mode is supported and the transmitter c ontrols the transfer clock. bit 3 ? txenn: transmitter enable writing this bit to ?1? enables the usart transmitter. when enabled, the transmitter overrides normal port operation for the txdn pin. disabling the transmitter does not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not co ntain data to be transmitted. when disabled, the transmitter no longer overrides the txdn pin. bit 7 6543210 rxcien txcien udrie rxenn txenn ? ? ? ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 0 0 0 attiny1634 [preliminary datasheet] 9296c?avr?07/14 168 bits 2:0 ? reserved bits in mspi mode in mspi mode these bits are reserved for future use. for compat ibility with future devices, these bits must be written as ?0?. 18.8.4 ucsrnc ? usartmspim control and status register n c bits 7:6 ? umseln[1:0]: usart mode select these bits select the operating mode of the usart as shown in table 18-4 . the mspim is enabled when both umsel bits are set to ?1?. for a full description of normal usart operation, see section 17.12.4 ?ucsrnc ? usart co ntrol and status register c? on page 159 . bits udordn, ucphan, and ucpoln may be set in the same write operation where the mspim is enabled. bits 5:3 ? reserved bits in mspi mode in mspi mode these bits are reserved for future use. for com patibility with future devices, thes e bits must be written as ?0?. bit 2 ? udordn: data order when set, the lsb of the data word is transmitted first. when cleared, the msb of the data word is transmitted first. for more information, see section 18.5 ?frame formats? on page 163 . bit 1 ? ucphan: clock phase this bit determines if data is sampled on the le ading (first), or trailing (last) edge of xckn. for more information, see section 18.4 ?spi data modes and timing? on page 163 . bit 0 ? ucpoln: clock polarity this bit sets the polarity of the xckn clock. the combinat ion of ucpoln and ucphan bits dete rmine the timing of the data transfer. for more information, see table 18-2 on page 163 . 18.8.5 ubrrnl and ubrrnh ? usart mspim baud rate registers the function and bit description of the baud rate register s in mspi mode are identical to normal usart operation (see section 17.12.6 ?ubrrnl and ubrrnh ? usart baud rate registers? on page 161 ). bit 7 6 543210 umseln1 umseln0 ? ? ? udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 18-4. umseln bit settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) 169 attiny1634 [preliminary datasheet] 9296c?avr?07/14 19. analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the vo ltage on the negative pin ain1, the analog comparator output (aco) is set. the comparator can trigger a separate interrupt that excludes the analog comparator. the user can select interrupt triggering on comparator output rise, fall, or toggle. a block diagram of the comparator and its related logic is shown in figure 19-1 . figure 19-1. analog comparator block diagram note: 1. see table 19-1 on page 169 . for information about pin placements, see figure 1-1 on page 3 . the adc power reduction bit (pradc) must be disabled in order to use the adc input multiplexer. this is done by clearing the pradc bit in the power reduction register (prr). for more information, see section 8.4.2 ?prr ? power reduction register? on page 37 . 19.1 analog comparator multiplexed input when the analog to digital converter (adc) is configured as a si ngle-ended input channel, it is possible to select any of the adc[11 : 0] pins to replace the negativ e input to the analog comparator. the adc mult iplexer is used to select this input; the adc must therefore be switched off to utilize this feature. if the analog co mparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (aden in adcsra is ?0?), mux[3 : 0], in admux select the input pin to replace the negative input to the analog comparator as shown in table 19-1 . if acme is cleared or aden is set, ain1 is applied to the analog comparator negative input. bandgap reference interrupt select ain0 vcc acis1 adc multiplexer output (1) acis0 acic aco acie analog comparator irq aci to t/c1 capture trigger mux acbg acme aden acd + - ain1 table 19-1. analog comparator multiplexed input acme aden analog comparator negative input 0 x ain1 1 0 adc multiplexer. see table 20-4 on page 183 1 1 ain1 attiny1634 [preliminary datasheet] 9296c?avr?07/14 170 19.2 register description 19.2.1 acsra ? analog comparator control and status register bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog compar ator is switched off. this bit can be set at any time to turn off the analog comparator. this reduces power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsra. otherwise, an interrupt can occur when the bit is changed. bit 6 ? acbg: analog comp arator band-gap select when this bit is set, a fixed internal band-gap reference voltage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to t he positive input of the analog comparator. bit 5 ? aco: analog comparator output the output of the analog compar ator is synchronized and then connected directly to aco. the synchronization introduces a delay of 1 to 2 clock cycles. bit 4 ? aci: analog comparator interrupt flag this bit is set by the hardware when a comparator output event triggers the inte rrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector . alternatively, aci is cleared by writing a logic one to the flag. bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i bit in the status register is set, the analog comparator interrupt is activate d. when written logic zero, the interrupt is disabled. bit 2 ? acic: analog compar ator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. in this case, the comparator output is connected directly to the in put capture front-end logic, making the comparator utilize the noise c anceler and edge select features of the timer/ counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and t he input capture function exists. to make the comparator trigger the timer/counter1 input capture in terrupt, the icie1 bit in th e timer interrupt mask register (timsk) must be set. bits 1:0 ? acis[1:0]: analog comparator interrupt mode select these bits determine which comparator event s trigger the analog comparator interrupt. the different settings are shown in table 19-2 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsra register. otherwise, an interrupt can occur when the bits are changed. bit 76543210 0x06 (0x26) acd acbg aco aci acie acic acis1 acis0 acsra read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 table 19-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 0 1 reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 171 attiny1634 [preliminary datasheet] 9296c?avr?07/14 19.2.2 acsrb ? analog comparator control and status register b bit 7 ? hsel: hysteresis select when this bit is written logic one, the hysteresis of the analog comparator is enabled. the level of hysteresis is selected by the hlev bit. bit 6 ? hlev: hysteresis level when enabled via the hsel bit, the level of hysteresis can be set using the hlev bit as shown in table 19-3 . bit 5 ? aclp this bit is reserved for qtouch and always writes as ?0?. bit 4 ? reserved this bit is reserved and always reads as ?0?. bit 3 ? acce this bit is reserved for qtouch and always writes as ?0?. bit 2 ? acme: analog comp arator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is ?0?), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see section 19.1 ?analog comparator multiplexed input? on page 169 . bit 1 ? acirs1 this bit is reserved for qtouch and always writes as ?0?. bit 0 ? acirs0 this bit is reserved for qtouch and always writes as ?0?. 19.2.3 didr0 ? digital input disable register bits 2:1 ? ain1d, ain0d: ain1 and ain0 digital input disable when this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corresponding pin register bit always reads as ?0? when this bit is set. when used as an analog input but not required as a digital input, the power consumption in the digital input buffer can be reduced by writing this bit to logic one. bit 7 6543210 0x05 (0x25) hsel hlev aclp ? acce acme acirs1 acirs0 acsrb read/write r/w r/w r/w r r/w r/w r/w r/w initial value0 0000000 table 19-3. selecting level of analog comparator hysteresis hsel hlev hysteresis of analog comparator 0 x not enabled 1 0 20mv 1 50mv bit 76543210 (0x60) adc4d adc3d adc2d adc1d adc0d ain1d ain0d arefd didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 172 20. analog to digital converter 20.1 features 10-bit resolution 1 lsb integral nonlinearity 2 lsb absolute accuracy 13 clocks conversion time 15ksps at maximum resolution 12 multiplexed single-ended input channels temperature sensor input channel optional left adjustment for adc result readout 0 - v cc adc input voltage range 1.1v adc reference voltage free-running or single-conversion mode adc start conversion by auto triggering on interrupt sources interrupt on adc conversion complete sleep mode noise canceler 20.2 overview the atmel ? attiny1634 features a 10-bit, successive approximation analog-to-digital converter (adc). the adc is wired to a 13-channel analog multiplexer, which allows the adc to meas ure the voltage at 12 single-ended input pins or from one internal single-ended voltage channel coming from the internal temperature sensor. single-ended voltage inputs are referred to 0v (gnd). the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 20-1 on page 173 . internal reference voltage of nominally 1.1v is provided on-chip. alternatively, v cc can be used as reference voltage for single-ended channels. there is also an option to use an exte rnal voltage reference and turn off the internal voltage reference. 173 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 20-1. analog to digital converter block schematic prescaler start bin adc12 - + 15 0 adc multiplexer select (admux) trigger select mux decoder v cc adts[2:0] 8-bit data bus interrupt flags aref 10-bit dac sample and hold comparator internal reference 1.1v temperature sensor conversion logic adc ctrl & status b register b (adcsrb) adc conversion complete irq adc ctrl and status register a (adcsra) adc data register (adch/adcl) adif aden channel selection adsc mux[4:0] refs[1:0] adlar adif adps2 adps1 adps0 adate adie adc[9:0] adc multiplexer output adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 agnd input mux adc8 adc9 adc10 adc11 attiny1634 [preliminary datasheet] 9296c?avr?07/14 174 20.3 operation to enable use of adc, the power reduction bit (pradc) in the power reduction register must be disabled. this is done by clearing the pradc bit. for more information, see section 8.4.2 ?prr ? power reduction register? on page 37 . the adc is enabled by setting the adc enable bit aden in a dcsra. voltage reference and input channel selections do not go into effect until aden is set. the adc does not consume power when aden is cleared; it is thus recommended to switch off the adc before entering power-saving sleep modes. the adc converts an analog input voltage to a 10-bit digital value using successive approximation. the minimum value represents gnd and the maximum value repr esents the reference voltage. the adc vo ltage reference is selected by writing the refs[1 : 0] bits in the admux regist er. alternatives are the v cc supply pin, the aref pin, and the internal 1.1v voltage reference. the analog input channel is selected by writing to the mux bi ts in admux. any of the adc input pins can be selected as single-ended inputs to the adc. the adc generates a 10-bit result which is presented in the adc data registers, adch, and adcl. the result is presented right-adjusted by default but can optio nally be presented left-adjusted by setting the adlar bit in adcsrb. if the result is left-adj usted and no more than 8-bit precision is required , it is sufficient to r ead adch only. otherwise adcl must be read first, then adch to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of ad ch and adcl, the interrupt triggers even if the result is lost. 20.4 starting a conversion make sure the adc is powered by clearing the adc power reduc tion bit (pradc) in the power reduction register (prr). for more information, see section 8.4.2 ?prr ? power reduction register? on page 37 . a single conversion is started by writing a logic one to the adc start conversion bit (adsc). this bit stays high as long as th e conversion is in progress and is cleared by hardware when th e conversion is completed. if a different data channel is selected while a conversion is in progress, the adc finishes the current conversion befor e performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit adate in adcsra. the trigger source is selected by setting the adc trigger select bits adts in adcsrb (see description of the adts bits for a list of trigger sources). when a posi tive edge occurs on the selected trigger signal, the adc prescaler is reset and a co nversion is started. this provides a method of star ting conversions at fixed intervals. if the trigger signal is still se t when the conversion comple tes, a new conversion is no t started. if another positi ve edge occurs on the trigger signal during conversion, the edge is ignored. note that an interrupt flag is set even if the specif ic interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in or der to trigger a new conversion at the next interrupt event. figure 20-2. adc au to trigger logic edge detector conversion logic prescaler adif adsc adate start clk adc adts[2:0] . . . . source 1 source n 175 attiny1634 [preliminary datasheet] 9296c?avr?07/14 using the adc interrupt flag as a trigger s ource forces the adc to start a new conver sion as soon as the ongoing conversion has finished. the adc then operates in free-running mode, constantly sampling and updating the adc data register. the first conversion must be started by writing a logic one to the adsc bit in adcsra. in this mode the adc performs successive conversions regardless of whether the adc interrupt flag (adif) is cleared or not. if auto triggering is enabled, single conver sions can be started by writing adsc in adcsra to ?1?. adsc can also be used to determine if a conversion is in progress. the adsc bit is read as ?1? during a conversion and does not depend on how the conversion was started. 20.5 prescaling and conversion timing by default, the successive appr oximation circuitry requires an input clock freq uency between 50khz and 200khz to achieve maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200khz to achieve a higher sample rate. it is not advisable to use a higher input clock frequency than 1mhz. figure 20-3. adc prescaler the adc module contains a prescaler, as illustrated in figure 20-3 , which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set and is continuously reset when aden is low. when initiating a single-ended conversion by setting the adsc bit in adcsra, the conversion starts at the next rising edge of the adc clock cycle. a normal conversion takes 13 ad c clock cycles as summarized in table 20-1 on page 177 . the first conv ersion after the adc is switched on (aden in adcsra is se t) and takes 25 adc clock cycles in orde r to initialize the analog circuitry as shown in figure 20-4 below. 7-bit adc prescaler adc clock source aden start ck adps0 adps1 adps2 reset ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 ck/128 attiny1634 [preliminary datasheet] 9296c?avr?07/14 176 figure 20-4. adc timing di agram, first conversion (single-conversion mode) the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of a first conversion (see figure 20-5 ). when a conversion is complete, the result is written to the adc data registers and adif is set. in single-conversion mode adsc is cleared simultaneously. the software may then set adsc again and a new conversion is initia ted on the first rising adc clock edge. figure 20-5. adc timing diag ram, single conversion when auto triggering is used, the prescaler is reset when the trigger event occurs as shown in figure 20-6 on page 177 . this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal . three additional cpu cl ock cycles are used for synchronization logic. 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 cycle number first conversion sign and msb of result lsb of result next conversion mux and refs update conversion complete mux and refs update adc clock aden adsc adif adch adcl sample and hold 12345678910111213 123 cycle number one conversion sign and msb of result lsb of result next conversion mux and refs update conversion complete mux and refs update adc clock adsc adif adch adcl sample and hold 177 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 20-6. adc timing diagram, auto triggered conversion in free-running mode a new conversion will be started immediat ely after the conversion completes while adsc remains high (see figure 20-7 ). figure 20-7. adc timi ng diagram, free-r unning conversion for a summary of conversion times, see table 20-1 . table 20-1. adc co nversion time condition sample and hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions 1.5 13 auto triggered conversions 2 13.5 free-running conversion 2.5 14 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 cycle number one conversion sign and msb of result lsb of result next conversion mux and refs update prescaler reset prescale r reset conversion complete adc clock trigger source adif adate adch adcl sample and hold 12 13 14 1 2 3 4 cycle number one conversion sign and msb of result lsb of result next conversion mux and refs update conversion complete adc clock adsc adif adch adcl sample and hold attiny1634 [preliminary datasheet] 9296c?avr?07/14 178 20.6 changing channel or reference selection the mux[3:0] and refs[1:0] bits in the admux register are single-buffered through a temporary register to which the cpu has random access. this ensures that the channels and refer ence selection only takes place at a safe point during the conversion. the channel and reference select ion is continuously updated until a conv ersion is started. once the conversion starts, the channel and reference selection is locked to ensur e there is sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycl e before the conversion completes (adi f in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. for this reason, the user is advised not to write new channel or reference sele ction values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggering event can be indetermin istic. special care must be taken when updating the admux register to check what c onversion is affected by the new settings. if both adate and aden are written to ?1?, an interrupt even t can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or th e new settings. admux can be safely updated in the following ways: when adate or aden are cleared during conversion, at least one a dc clock cycle after the trigger event after a conversion, before the interrupt fl ag used as the trigger source is cleared when updating admux in one of these conditions, the new settings will affect the next adc conversion. 20.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single-conversion mode always select the channel be fore starting the conversion. the channel selection may be changed one adc clock cycle after writing ?1? to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free-running mode always select the channel before star ting the first conversion. the channel selection may be changed one adc clock cycle after writing ?1? to adsc. howe ver, the simplest method is to wait for the first conversion to complete and then change the channel sele ction. because the next conversion has already started automatically, the next re sult reflects the previous channel selection. subsequent conversions reflect the new channel selection. 20.6.2 adc voltage reference the adc reference voltage (v ref ) indicates the conversion range for the adc. single-ended channels that exceed v ref result in codes close to 0x3ff. v ref can be selected as v cc , internal 1.1v reference, or exte rnal aref pin. the internal 1.1v reference is generated from the internal band-gap reference (v bg ) through an internal amplifier. the first adc conversion result after sw itching reference voltage source may be ina ccurate; the user is advised to discard this result. 20.7 adc noise canceler the adc features a noise canceler that enables conversion duri ng sleep mode. this feature re duces noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the follow ing procedure should be used: make sure that the adc is enabled and is not busy co nverting. single-conversion m ode must be selected and the adc conversion complete interrupt must be enabled. enter adc noise reduction mode (or idle mode). the adc starts a conversion once the cpu has been stopped. if no other interrupts occur before the adc conversion co mpletes, the adc interrupt wa kes up the cpu and executes the adc conversion complete interrupt routine. if anot her interrupt wakes up the cpu before the adc conversion is complete, that interrupt is executed and an adc conversi on complete interrupt request is generated when the adc conversion completes. the cpu remains in active mode until a new sleep command is executed. note that the adc is not automatically turned off when ente ring sleep modes other than idle mode and adc noise reduction mode. the user is advised to write ?0? to aden before entering such sleep modes to avoid excessive power consumption. 179 attiny1634 [preliminary datasheet] 9296c?avr?07/14 20.8 analog input circuitry the analog input circuitry for single-ended channels is illustrated in figure 20-8 . an analog source applied to adcn is subjected to the pin capacitance and input l eakage of that pin, regardless of whether t hat channel is selected as input for the adc or not. when the channel is selected, the source must dr ive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wi th an output impedance of approximately 10k or less. if such a source is used, the sampling time is negligible. if a source with higher im pedance is used, the sampling time depends on how much time the source needs for charging the s/h capacitor; this time can va ry widely. the user is recommended to only use low impedance sources with slowly varying signals because this minimi zes the required charge transfer to the s/h capacitor. in order to avoid distortion from unpredictable signal conv olution, signal components high er than the nyquist frequency (f adc /2) should not be present. the user is advised to remo ve high-frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 20-8. analog input circuitry note: the capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. the value given is worst case. 20.9 noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. when conversion accuracy is critical, the noise level can be reduced by applying the following techniques: keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane. keep analog tracks well away from high-speed switching digital tracks. if any port pin is used as a digital output, it sh ould never switch while a conversion is in progress. place bypass capacitors as close to v cc and gnd pins as possible. where high adc accuracy is required, it is recomm ended to use adc noise reduction mode as described in section 20.7 ?adc noise canceler? on page 178 . this is especially the case when system cl ock frequency is above 1mhz or when the adc is used for reading the internal temperature sensor as described in section 20.12 ?temperature measurement? on page 182 . a good system design with properly placed external bypa ss capacitors reduces the need for using adc noise reduction mode. i il v cc /2 c s/h = 14pf i ih adcn 1 to 100k attiny1634 [preliminary datasheet] 9296c?avr?07/14 180 20.10 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as ?0? and the highest code as ?2 n -1?. several parameters describe the deviation from the ideal behavior as follows: offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 20-9. offset error gain error: after adjusting for offset, the gain error is foun d as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 20-10. gain error offset error output code ideal adc actual adc v ref input voltage output code ideal adc actual adc v ref input voltage gain error 181 attiny1634 [preliminary datasheet] 9296c?avr?07/14 integral nonlinearity (inl): after adjust ing for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 20-11. integral nonlinearity (inl) differential nonlinearity (dnl): the maximum deviation of t he actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 20-12. differential nonlinearity (dnl) quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) codes to the same value. always 0.5 lsb. absolute accuracy: the maximum deviation of an actual (una djusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, di fferential error, nonlinearity, and quantization error. ideal value: 0.5 lsb. output code ideal adc inl actual adc v ref input voltage output code 0x3ff 0x000 0 1 lsb dnl v ref input voltage attiny1634 [preliminary datasheet] 9296c?avr?07/14 182 20.11 adc conversion result after the conversion is complete (adif is high), the conver sion result can be found in th e adc data registers (adcl, adch). for single-ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 20-3 on page 183 and table 20-4 on page 183 ). 0x000 represents analog ground and 0x3ff repr esents the selected reference voltage minus one lsb. the result is presented in one-sided form, from 0x3ff to 0x000. 20.12 temperature measurement temperature measurement is based on an on-chip sensor, coupled to a single-ended adc channel. the temperature sensor is enabled when channel adc12 is selected from the admux register. when measuring temperature, the internal voltage reference must be selected as the adc reference source. when enabled, the adc converter can be used in single- conversion mode to measure the volt age over the temperature sensor. the measured voltage has a linear relationship to temperature as shown in table 20-2 . the sensitivity is approximately 1 lsb/c and the accuracy depends on the method of user ca libration. the temperature sensor should be calibrated by firmware in order to achieve reasonable accuracy. typica lly, the measurement accuracy after a single temperature calibration is 10 c assuming calibration at room temp erature. better accuracies are ac hieved by using two temperature points for calibration. the values described in table 20-2 are typical values. due to process variat ion, however, the output voltage of the temperature sensor varies from one chip to another. to ac hieve more accurate results, temperature measurements can be calibrated in the application software. the soft ware calibration can be done using the equation: t = k [(adch << 8) | adcl] + t os where adch and adcl are the adc data register s, k is the fixed slope coefficient, and t os is the temperature sensor offset. typically, k is very close to 1.0 and in single -point calibration the coefficient may be omitted. 20.13 register description 20.13.1 admux ? adc multip lexer select ion register bits 7:6 ? refs[1:0]: reference selection bits these bits select the voltage reference for the adc as shown in table 20-3 on page 183 . adc v in 1024 v ref --------------------------- = table 20-2. temperature versus sens or output voltage (typical) temperature ?40 c +25 c +85 c adc 235 lsb 300 lsb 360 lsb bit 76543210 0x04 (0x24) refs1 refs0 refen adc0en mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 183 attiny1634 [preliminary datasheet] 9296c?avr?07/14 if these bits are changed during a conversion , the change does not go into effect until this conversion is complete (adif in adcsr is set). also note that when these bits are changed, the next conversion takes 25 adc clock cycles. it is recommended to force the adc to perform a long conver sion when changing multiplexer or voltage reference settings. this can be done by first turning off the adc, then changing re ference settings, and then turning on the adc. alternatively, the first conversion results after changing reference settings should be discarded. internal voltage reference options sh ould not be used if an external voltage is being applied to the aref pin. bit 5 ? refen this bit is reserved for qtouch and always writes as ?0?. bit 4 ? adc0en this bit is reserved for qtouch and always writes as ?0?. bits 3:0 ? mux[3:0]: analog channel and gain selection bits the value of these bits selects which combination of analog inputs are connected to the adc as shown in table 20-4 . selecting the channel adc12 enables the temperature measurement (see table 20-4 ). notes: 1. after switching to internal voltage reference, the a dc requires a settling time of 1ms before measurements are stable. conversions starting before this may not be reli able. the adc must be enabled during the settling time. 2. see section 20.12 ?temperature measurement? on page 182 . if these bits are changed during a conversi on, the change does not go into effect until the conversion is complete (adif in adcsra is set). table 20-3. voltage refere nce selections for adc refs1 refs0 voltage reference selection 0 0 v cc used as analog reference, disconnected from pa0 (aref) 0 1 external voltage reference at pa0 (aref) pin 1 0 internal 1.1v voltage reference 1 1 reserved table 20-4. single-ended input channel selections. mux[3:0] single-ended input pin 0000 adc0 pa3 0001 adc1 pa4 0010 adc2 pa5 0011 adc3 pa6 0100 adc4 pa7 0101 adc5 pb0 0110 adc6 pb1 0111 adc7 pb2 1000 adc8 pb3 1001 adc9 pc0 1010 adc10 pc1 1011 adc11 pc2 1100 ground gnd 1101 internal 1.1v reference (1) (internal) 1110 temperature sensor (2) (internal) 1111 reserved not connected attiny1634 [preliminary datasheet] 9296c?avr?07/14 184 20.13.2 adcsra ? adc control and status register a bit 7 ? aden: adc enable writing this bit to ?1? enables the adc. wr iting it to ?0? turns adc off. turning t he adc off while a conversion is in progress terminates this conversion. bit 6 ? adsc: adc start conversion in single-conversion mode write this bit to ?1? to start each co nversion. in free-running mode write this bit to ?1? to start t he first conversion. the first conversion after adsc has been writt en after the adc has been enabled or if adsc is written at the same time as the adc is e nabled. it takes 25 adc clock cycles instead of the normal 13 . this first conversion performs initialization of the adc. adsc reads as ?1? as long as a conversion is in progress. when the conversion is complete, it returns to ?0?. writing ?0? to this bit has no effect. bit 5 ? adate: adc auto trigger enable when this bit is written to ?1?, auto tr iggering of the adc is enabled. the adc star ts a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits adts in adcsrb. bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and th e data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i bit in sreg are set. adif is cl eared by the hardware when executing the corresponding interrupt handling vector. alternatively, adif is cleared by writing a logic one to the flag. beware that doing a read-modify-write on adcsra may cause a pending interrupt to be disabled. this also applies if the sbi instruction is used. bit 3 ? adie: adc interrupt enable when this bit is written to ?1? and the i bit in sreg is set, the adc conversion comp lete interrupt is activated. bits 2:0 ? adps[2:0]: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. bit 76543210 0x03 (0x23) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 20-5. adc prescaler selections adps2 adps1 adps0 division factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 185 attiny1634 [preliminary datasheet] 9296c?avr?07/14 20.13.3 adcl and adch ? adc data register 20.13.3.1 adlar = 0 20.13.3.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated until adch is read. if the result is left-adjusted and no more than 8-bit precision is required, it is theref ore sufficient to read adch. otherwise, adcl must be read first and then adch. the adlar bit in adcsrb and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left-adjusted. if adlar is cleared (default), the re sult is right-adjusted. adc[9:0]: adc conversion result these bits represent the result fr om the conversion as detailed in section 20.11 ?adc conversion result? on page 182 . 20.13.4 adcsrb ? adc control and status register b bit 7 ? vden this bit is reserved for qtouch and always writes as ?0?. bit 6 ? vdpd this bit is reserved for qtouch and always writes as ?0?. bits 5:4 ? res: reserved bits these are reserved bits in atmel ? attiny1634. for compatibility with future devices, always write these bits to ?0?. bit 151413121110 9 8 0x01 (0x21) ? ? ? ? ? ? adc9 adc8 adch 0x00 (0x20) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 0x01 (0x21) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch 0x00 (0x20) adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 76543210 0x02 (0x22) vden vdpd ? ? adlar adts2 adts1 adts0 adcsrb read/write r/w r/w r r r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 186 bit 3 ? adlar: adc left-adjust result the adlar bit affects the presentation of th e adc conversion result in the adc data register. write ?1? to adlar to left- adjust the result. otherwise, the result is right-adjusted. changing the adlar bit affe cts the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see section 20.13.3 ?adcl and adch ? adc data register? on page 185 . bits 2:0 ? adts[2:0]: adc auto trigger source if adate in adcsra is written to ?1?, t he value of these bits selects what source triggers an adc conversion. if adate is cleared, the adts[2:0] settings have no effect. a conversion is triggered by the rising edge of the selected interrupt flag. note that switching from a trigger source that is cleared to a trigger source that is set gener ates a positive edge on the trig ger signal. if aden in adcsra is set, this starts a conversion. switching to free-running mode (adts[2:0]=0) does not cause a trigger event even if the adc interrupt flag is set . 20.13.5 didr0 ? digital input disable register 0 bits 7:3 ? adc4d:adc0d: adc[4:0] digital input disable when a bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit always reads as ?0? when this bit is set. when an analog signal is applied to the adc[7 : 0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 20.13.6 didr1 ? digital input disable register 1 bits 3:0 ? adc8d:adc5d: adc[8:5] digital input disable when a bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit always reads as ?0? when this bit is set. when an analog signal is applie d to the adc[8:5] pin and the digital inp ut from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 20-6. adc auto trig ger source selections adts2 adts1 adts0 trigger source 0 0 0 free-running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 (0x60) adc4d adc3d adc2d adc1d adc0d ain1d ain0d arefd didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x61) ? ? ? ? adc8d adc7d adc6d adc5d didr1 read/write r r r r r/w r/w r/w r/w initial value00000000 187 attiny1634 [preliminary datasheet] 9296c?avr?07/14 20.13.7 didr2 ? digital input disable register 2 bits 2:0 ? adc11d:adc9d: adc[ 11:9] digital input disable when a bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit always reads as ?0? when this bit is set. when an analog signal is applied to the adc[11 : 9] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer . bit 76543210 (0x62) ? ? ? ? ? adc11d adc10d adc9d didr2 read/write r r r r r r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 188 21. debugwire on-chip debug system 21.1 features complete program flow control emulates all on-chip functions, both digital and analog, except reset pin real-time operation symbolic debugging support (both at c and assembler source level, or for other hlls) unlimited number of program break points (using software break points) non-intrusive operation electrical characteristics identical to real device automatic configuration system high-speed operation programming of nonvolatile memories 21.2 overview the debugwire on-chip debug system uses a one-wire bidire ctional interface to control the program flow, execute avr ? instructions in the cpu, and progra m the different nonvolatile memories. 21.3 physical interface when the debugwire enable (dwen) fuse is programmed an d lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open -drain) bidrectional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 21-1 shows the schematic of a target mcu with debugwire enabled and the emulator connector. the system clock is not affected by debugwire an d is always the clock source selected by the cksel fuses. figure 21-1. the debugwire setup when designing a system where debugwire is used, the following must be observed: the pull-up resistor on the dw/(reset ) line must be in the range of 10k to 20k . however, the pull-up resistor is optional. connecting the reset pin directly to v cc does not work. capacitors inserted on the reset pin must be disconnected when using debugwire. all external reset sources must be disconnected. gnd 2.7 - 5.5v dw vcc dw (reset) 189 attiny1634 [preliminary datasheet] 9296c?avr?07/14 21.4 software break points debugwire supports program memory break points by the avr ? break instruction. setting a break point in avr studio ? inserts a break instruction in the prog ram memory. the instruction replaced by the break instruction is stored. when program execution is continued, the stored instruction is executed before c ontinuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be reprogrammed each time a break point is changed. this is au tomatically handled by avr studio through the debugwire interface. the use of break points thus re duces the flash data retention. devices used for debugging purposes should not be shipped to end customers. 21.5 limitations of debugwire the debugwire communication pin (dw) is physically located on the same pin as the external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately em ulates all i/o functions when running at full sp eed, i.e., wh en the program in the cpu is running. when the cpu is stopped, care must be taken wh ile accessing some of the i/o registers via the debugger (avr studio). see the debugwire documentation for more information about the limitations. the debugwire interface is asynchronous , which means that the debugger needs to synchronize to the system clock. if the system clock is changed by software (e.g., by writing clkps bits), communication via debugwire may fail. in addition, clock frequencies below 100khz may cause communication problems. a programmed dwen fuse enables some parts of the clock syst em to run in all sleep modes. this increases the power consumption while in sleep. the dwen fuse should therefore be disabled when debugwire is not used. 21.6 register description the following section describes th e registers used with the debugwire. 21.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible via the debugwire and therefore cannot be us ed as a general purpose register in normal operations. bit 76543210 0x2e (0x4e) dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 attiny1634 [preliminary datasheet] 9296c?avr?07/14 190 22. self programming 22.1 features self programming enables mcu to erase, write, and reprogram application memory efficient read-modify-write support lock bits allow application memory to be securely closed for further access 22.2 overview the device provides a self programming mechanism for do wnloading and uploading the program code by the mcu itself. self programming can use any available dat a interface and associated protocol to read code and write (program) that code into program memory. 22.3 lock bits program memory can be protected from internal or external access (see section 23.1 ?lock bits? on page 196 ). 22.4 self programming the flash program memory is updated in a page-by-page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the ?4-page erase? command or between a 4-page erase and a page write operation: 1. either, fill the buffer before a 4-page erase: a. fill temporary page buffer b. perform a 4-page erase c. perform a page write 4. or, fill the buffer after a 4-page erase: a. perform a 4-page erase b. fill temporary page buffer c. perform a page write the ?4-page erase? command erases four pr ogram memory pages at the same time. if only part of this section needs to be changed, the rest must be stored be fore the erase and then re-written. the temporary page buffer can be accessed in a random sequence. the spm instruction is disabled by default but it c an be enabled by programming the selfprgen fuse (to ?0?). 191 attiny1634 [preliminary datasheet] 9296c?avr?07/14 22.4.1 addressing the flash during self programming the z pointer is used to address the spm commands. because the flash is organized in pages (see table 24-1 on page 202 ), the program counter can be treated as having two different sections. one section, consisti ng of the least significant bits, addre sses the words within a page while the most significant bits address the pages. this is shown in figure 22-1 . figure 22-1. addressing the flash during spm load and write operations bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 pagemsb pcmsb zpcmsb 15 1 0 0 z-register bit zpagemsb word address within a page page address within the flash pcword pcpage page program memory program counter 02 01 00 pageend pcword [pagemsb : 0] page instruction word attiny1634 [preliminary datasheet] 9296c?avr?07/14 192 the ?4-page erase? command addresses several pr ogram memory pages simultaneously as shown in figure 22-2 . figure 22-2. addressing the flash during spm 4-page erase variables used in the figures above are explained in table 22-1 . note that 4-page erase and page write operations address memo ry independently. the software must therefore ensure the page write command addresses a page previously erased by the ?4-page erase? command. although the least significant bit of the z register (z0) shou ld be ?0? for spm, it should be not ed that the lpm instruction addresses the flash byte-by-byte and uses z0 as a byte select bit. once a programming operation is initia ted, the address is latched and the z po inter can be used for other operations. table 22-1. variables used in flash addressing variable description pcpage program counter page address. selects the program memory page for page load and page write commands. selects a block of program pages for the 4-page erase operation. see table 24-1 on page 202 . pcmsb the most significant bit of the program counter. see table 24-1 on page 202 . zpcmsb the bit in the z register that is map ped to pcmsb. because z[0] is not used, zpcmsb = pcmsb + 1. z register bits above zpcmsb are ignored. pcword program counter word address. selects the word within a page. this is used for filling the temporary buffer and must be ?0? during page write operations. see table 24-1 on page 202 . pagemsb the most significant bit used to address the word within one page. zpagemsb the bit in the z register that is mapped to pagemsb. because z[0] is not used, zpagemsb = pagemsb + 1. pagemsb pcmsb zpcmsb 15 1 0 0 z-register bit zpagemsb page address within the flash pcword pcpage page program memory program counter 193 attiny1634 [preliminary datasheet] 9296c?avr?07/14 22.4.2 4-page erase this command erases four pages of pr ogram memory. to execute 4-page erase: set up the address in the z pointer. write ?00000011? to spmcsr. execute an spm instruction within f our clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be wr itten to pcpage in the z regi ster. pcpage[1:0] is ignored, as are other bits in the z pointer. the cpu is stopped during the 4-page erase operation. 22.4.3 page load to write an instruction word: set up the address in the z pointer. set up the da ta in r1:r0. write ?00000001? to spmcsr. execute an spm instruction within f our clock cycles after writing spmcsr. the content of pcword in the z register is used to address th e data in the temporary buffer. the temporary buffer will auto erase after a page write operation or by writing the ctpb bit in spmcsr. it is also erased after a system reset. note that it is not possible to wr ite more than one time to each addre ss without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 22.4.4 page write to execute page write: set up the address in the z pointer. write ?00000101? to spmcsr. execute an spm instruction within f our clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be wr itten to pcpage. other bits in the z pointer must be written to ?0? during this operation. the cpu is stopped during the page write operation. 22.4.5 spmcsr cannot be writte n when eeprom is programmed note that an eeprom write operation blocks all software programming to flash. r eading fuses and lock bits from software is also prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in eecr and verifies that it is cl eared before writing to spmcsr. 22.5 preventing flash corruption during periods of low v cc , the flash program may be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board-level systems using flash and the same design solutions should be applied. a flash program corruption can be caused by two situations wh en the voltage is too low. firs t, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondl y, if the supply voltage for ex ecuting instructions is too low, the cpu itself can execute instructions incorrectly. attiny1634 [preliminary datasheet] 9296c?avr?07/14 194 flash corruption can easily be avoided by followin g these design recommendations (one is sufficient): 1. keep the avr ? reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the o perating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation is completed provided that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low v cc . this keeps the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register, and thus the flash from uninten- tional writes. 22.6 programming time for flash when using spm flash access is timed using the internal calibrated 8mhz osci llator. typical flash programming times for the cpu are shown in table 22-2 . note: 1. min. and max. programming times are per individual operation. 22.7 register description 22.7.1 spmcsr ? store program memory control and status register the store program memory control and status register contai ns the control bits needed to control the program memory operations. bits 7:6 ? res: reserved bits these bits are reserved and always read as ?0?. bit 5 ? rsig: read device signature imprint table issuing an lpm instruction within three cycles after rsig and spmen bits have been set returns the selected data (depending on z pointer value) from the device signat ure imprint table into the destination register (see section 23.3 ?device signature imprint table? on page 199 ). bit 4 ? ctpb: clear temporary page buffer if the ctpb bit is written while filling the temporary page buffer , the temporary page buffer is cleared and the data is lost. bit 3 ? rflb: read fuse and lock bits an lpm instruction within three cycles after rflb and spmen ar e set in the spmcsr register r eads either the lock bits or the fuse bits (depending on z0 in the z pointer) into the destination register. for more information, see section 22.4.5 ?spmcsr cannot be written when eeprom is programmed? on page 193 . bit 2 ? pgwrt: page write if this bit is written to ?1? at the same time as spmen, the next spm instruction within four clock cycles executes page write while storing the data in the temporary buffer. the page address is taken from the high part of the z pointer. the data in r1 and r0 are ignored. the pgwrt bit auto clears upon completion of a page write or if no spm in struction is executed within four clock cycles. the cpu is stopped during the entire page write operation. table 22-2. spm programming time operation min (1) max (2) spm: flash 4-page erase, flash page write, and lock bit write 3.7ms 4.5ms bit 7 65 4 3 210 0x37 (0x57) ? ? rsig ctpb rflb pgwrt pgers spmen spmcsr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 195 attiny1634 [preliminary datasheet] 9296c?avr?07/14 bit 1 ? pgers: page erase an spm instruction within four clock cycles of pgers and spm en have been set starts 4-page erase. the page address is taken from the high part of the z pointer. data in r1 and r0 are ignored. this bit auto clears upon completion of a 4-page erase or if no spm instruction is exec uted within four clock cycles. the cp u is stopped during t he entire 4-page erase operation. bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycl es. if set to ?1? together with rsig, ctpb, rflb, pgwrt, or pgers, the following lpm/spm instruction has a special meaning as described elsewhere. if only spmen is written, the following spm instruction will store the value in r1 :r0 in the temporary page buffer addressed by the z pointer. the lsb of the z pointer is ignored. the spmen bit auto clears upon completion of an spm instruction or if no spm instruction is executed within four clock cycles. duri ng 4-page erase and page write, the spmen bit remains high until the operation is completed. attiny1634 [preliminary datasheet] 9296c?avr?07/14 196 23. lock bits, fuse bits and device signature 23.1 lock bits the atmel ? attiny1634 provides the program and data memory lock bits listed in table 23-1 . note: 1. ?1? means unprogrammed, ?0? means programmed. lock bits can be left unprogrammed (?1?) or can be progra mmed (?0?) to obtain the additional features listed in table 23-2 . notes: 1. ?1? means unprogrammed, ?0? means programmed. 2. program fuse bits before programming lb1 and lb2. when programming the lock bits, the mode of protection can be increased only. wr iting the same, or lower, mode of protection automatically resu lts in maximum protection. lock bits can be erased to ?1? with the chip erase command only. the atmel attiny1634 has no separate boot loader section. the spm instruction is enabled for the whole flash if the selfprgen fuse is programmed (?0?), otherwise it is disabled. table 23-1. lock bit byte lock bit byte bit no description see default value (1) ? 7 ? 1 (unprogrammed) ? 6 ? 1 (unprogrammed) ? 5 ? 1 (unprogrammed) ? 4 ? 1 (unprogrammed) ? 3 ? 1 (unprogrammed) ? 2 ? 1 (unprogrammed) lb2 1 lock bit below 1 (unprogrammed) lb1 0 1 (unprogrammed) table 23-2. lock bit protection modes lock bits (1) mode of protection lb2 lb1 1 1 no memory lock features enabled. 1 0 further programming of flash and eeprom is di sabled in parallel a nd serial programming mode. fuse bits are locked in both serial and parallel programming mode (2) . 0 1 reserved 0 0 further reading and programming of flash an d eeprom is disabled in parallel and serial programming mode. fuse bits are locked in both serial and parallel programming mode (2) . 197 attiny1634 [preliminary datasheet] 9296c?avr?07/14 23.2 fuse bits fuse bits are described in table 23-3 , table 23-4 , and table 23-5 . note that programmed fuses read as ?0?. notes: 1. programming this fuse bit changes the functionality of the reset pin and renders further programming via the serial interface impossible. the fuse bit can be unprogrammed using the parallel programming algorithm (see section 24.2 ?parallel programming? on page 202 ). 2. this fuse bit is not accessible in serial programming mode. 3. this setting enables spi programming. 4. this setting does not preserve eeprom. table 23-3. extended fuse byte bit # bit name use see default value 7 ? ? 1 (unprogrammed) 6 ? ? 1 (unprogrammed) 5 ? ? 1 (unprogrammed) 4 bodpd1 sets bod operating mode when device is in sleep modes other than idle table 9-2 on page 42 0 (unprogrammed) 3 bodpd0 1 (unprogrammed) 2 bodact1 sets bod operating mode when device is active or idle table 9-1 on page 42 1 (unprogrammed) 1 bodact0 0 (unprogrammed) 0 selfprgen enables spm instruction section 22. on page 190 1 (unprogrammed) table 23-4. high fuse byte bit # bit name use see default value 7 rstdisbl disables external reset (1) section 9.2.2 on page 40 1 (unprogrammed) 6 dwen enables debugwire (1) section 21. on page 188 1 (unprogrammed) 5 spien enables serial programming and downloading of data to device (2) 0 (programmed) (3) 4 wdton sets watchdog timer permanently on section 9.5.2 on page 45 1 (unprogrammed) 3 eesave preserves eeprom memory during chip erase operation section 24.2.3 on page 204 1 (unprogrammed) (4) 2 bodlevel2 sets bod trigger level table 25-7 on page 219 1 (unprogrammed) 1 bodlevel1 0 (programmed) 0 bodlevel0 1 (unprogrammed) attiny1634 [preliminary datasheet] 9296c?avr?07/14 198 note: 1. unprogramming this fuse at low voltages may result in overclocking. see section 25.3 ?speed? on page 217 for device speed versus supply voltage. 2. this setting results in maximum start-up time for the default clock source. 3. this setting selects the clock source described in section 7.2.2 ?calibrated internal 8mhz oscillator? on page 27 . fuse bits are locked when lock bit 1 (lb1) is programmed. t herefore, fuse bits must be programmed before lock bits. fuse bits are not affected by a chip erase. 23.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values have no effect until the part leaves the programming mode. this does not apply to the eesave fuse, which takes effect once it is programmed. the fuses are also latched on power-up in normal mode. table 23-5. low fuse byte bit # bit name use see default value 7 ckdiv8 divides clock by 8 (1) section 7.3 on page 28 0 (programmed) 6 ckout outputs system clock on port pin section 7.4 on page 28 1 (unprogrammed) 5 ? ? 1 (unprogrammed) 4 sut sets system start-up time table 7-2 on page 29 0 (programmed) (2) 3 cksel3 selects clock source table 7-3 on page 30 0 (programmed) (3) 2 cksel2 0 (programmed) (3) 1 cksel1 1 (unprogrammed) (3) 0 cksel0 0 (programmed) (3) 199 attiny1634 [preliminary datasheet] 9296c?avr?07/14 23.3 device signature imprint table the device signature imprint table is a dedicated memory ar ea used for storing miscellaneous device information such as the device signature and oscillator calibratio n data. most of this memory segment is reserved for internal use as outlined in table 23-6 . byte addresses are used when the device itself reads the data with the lpm comman d. external programming devices must use word addresses. notes: 1. for more information, see section 23.3.1 ?signature bytes? on page 199 . 2. for more information, see section 23.3.2 ?calibration bytes? on page 199 . 23.3.1 signature bytes all atmel ? microcontrollers have a three-byte signat ure code which identifies the device. th is code can be read in both serial and parallel mode, also when the device is locked. signature bytes can also be read by the device firmware. for more information, see section 23.4 ?reading lock, fuse, and signature data from software? on page 200 . the three signature bytes reside in a separate address space called the device signature impr int table. the signature data for the atmel attiny1634 is given in table 23-7 . 23.3.2 calibration bytes the device signature imprint table of the atmel attiny1634 contains calibration data for the internal oscillators as shown in table 23-6 on page 199 . during reset, calibration data is automatica lly copied to the calibrat ion registers (osccal0, osccal1) to ensure correct frequency of the calibrated oscillators (see section 7.5.3 ?osccal0 ? oscillator calibration register? on page 32 , and section 7.5.6 ?osccal1 ? oscillator calibration register? on page 33 ). calibration bytes can also be read by the dev ice firmware. for more information, see section 23.4 ?reading lock, fuse, and signature data from software? on page 200 . table 23-6. contents of devi ce signature imprint table word address (external) byte address (internal) description 0x00 0x00 signature byte 0 (1) 0x01 calibration data for internal 8mhz oscillator (osccal0) (2) 0x01 0x02 signature byte 1 (1) 0x03 oscillator temperature calibration data (osctcal0a) 0x02 0x04 signature byte 2 (1) 0x05 oscillator temperature calibration data (osctcal0b) 0x03 0x06 reserved 0x07 calibration data for internal 32khz oscillator (osccal1) (2) 0x04...0x3f ... reserved ... reserved table 23-7. device signature bytes part signature byte 0 signature byte 1 signature byte 0 atmel attiny1634 0x1e 0x94 0x12 attiny1634 [preliminary datasheet] 9296c?avr?07/14 200 23.4 reading lock, fuse, and signature data from software fuse and lock bits can be read by the device firmware. prog rammed fuse and lock bits read as ?0?, unprogrammed fuse and lock bits read as ?1? (see section 23.1 ?lock bits? on page 196 and section 23.2 ?fuse bits? on page 197 ). in addition, firmware can also read data from the device signature imprint table (see section 23.3 ?device signature imprint table? on page 199 ). 23.4.1 lock bit read lock bit values are returned in the destination r egister after an lpm instruction ha s been issued within three cpu cycles after rflb and spmen bits have been set in spmcsr (see section 22.7.1 ?spmcsr ? store program memory control and status register? on page 194 ). the rflb and spmen bits automatically clear upon completion of reading the lock bits, or if no lpm instruction is executed within three cpu cycles, or if no spm instru ction is executed within four cpu cycles. when rflb and spmen are cleared, lpm functions normally. follow the procedure below to read the lock bits: 1. load the z pointer with 0x0001. 2. set rflb and spmen bits in spmcsr. 3. issue an lpm instructio n within three clock cycles. 4. read the lock bits from the lpm destination register. if successful, the contents of the destination register are as follows: for more information, see section 23.1 ?lock bits? on page 196 . 23.4.2 fuse bit read the algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses are different. follow the procedure below to read the fuse low byte (flb): 1. load the z pointer with 0x0000. 2. set rflb and spmen bits in spmcsr. 3. issue an lpm instructio n within three clock cycles. 4. read the flb from the lpm destination register. if successful, the contents of the destination register are as follows: for a detailed description and mapping of the fuse low byte, see table 23-5 on page 198 . to read the fuse high byte (fhb), replace the address in the z pointer with 0x0003 and repeat the procedure above. if successful, the contents of the destination register are as follows: for a detailed description and mapping of the fuse high byte, see table 23-4 on page 197 . to read the fuse extended byte (feb), replace the address in the z pointer with 0x0002 and repeat the previous procedure. if successful, the contents of the destination register are as follows: for a detailed description and mapping of the fuse extended byte, see table 23-3 on page 197 . bit 76543210 rd ??????lb2lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd feb7 feb6 feb5 feb4 feb3 feb2 feb1 feb0 201 attiny1634 [preliminary datasheet] 9296c?avr?07/14 23.4.3 device signature imprint table read follow the procedure below to read the contents of the device signature imprint table: 1. load the z pointer with the table index. 2. set rsig and spmen bits in spmcsr. 3. issue an lpm instructio n within three clock cycles. 4. read table data from the lpm destination register. if successful, the contents of the destination register are as described in section 23.3 ?device signature imprint table? on page 199 . see program example below. note: see section 4.2 ?code examples? on page 7 . assembly code example dsit_read: ; uses z-pointer as table index ldi zh, 0 ldi zl, 1 ; preload spmcsr bits into r16, then write to spmcsr ldi r16, (1< 203 attiny1634 [preliminary datasheet] 9296c?avr?07/14 signals are described in table 24-3 . pins not listed in the table are referenced by pin names. pulses are assumed to be at least 250ns, unless otherwise noted. the xa1 and xa0 pins determine the action when clki is given a positive pulse as shown in table 24-5 . when pulsing wr or oe , the command loaded determines the action exec uted. the different command options are shown in table 24-6 . table 24-3. pin and signal names used in programming mode signal name pin(s) i/o function rdy/bsy pc2 o 0: the device is busy programming 1: the device is ready for new command oe pc1 i output enable (active low) wr pc0 i write pulse (active low) bs1/pagel pb3 i byte select 1 (0: low byte, 1: high byte) / program memory and eeprom data page load xa0 pb2 i xtal action bit 0 xa1/bs2 pb1 i xtal action bit 1/ byte select 2 (0: low byte, 1: 2 nd high byte) data i/o pa[7:0] i/o bidirectional data bus. output when oe is low table 24-4. pin values used to enter programming mode pin symbol value wr prog_enable[3] 0 bs1 prog_enable[2] 0 xa0 prog_enable[1] 0 xa1 prog_enable[0] 0 table 24-5. xa1 and xa0 coding xa1 xa0 action when clki is pulsed 0 0 load flash or eeprom address (high or low address byte, determined by bs1) 0 1 load data (high or low data byte for flash, determined by bs1) 1 0 load command 1 1 no action, idle table 24-6. command byte bit coding command byte command 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom attiny1634 [preliminary datasheet] 9296c?avr?07/14 204 24.2.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) programming mode: 1. set prog_enable pins (see table 24-4 on page 203 ) to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5v to 5.5v between v cc and gnd. ensure that v cc reaches at least 1.8v within the next 20s. 3. wait 20s to 6 0s and apply 11.5v to 12.5v to reset . 4. keep the prog_enable pins unchanged for at least 10s after the high voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300s before giving any parallel programming commands. 6. exit programming mode by powering th e device down or by bringing reset pin to 0v. if the rise time of the v cc is unable to fulfill the requirements listed above, the following alternative algorithm can be used: 1. set prog_enable pins ( table 24-4 on page 203 ) to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5v to 5.5v between v cc and gnd. 3. monitor v cc , and as soon as v cc reaches 0.9v to 1.1v a pply 11.5v to 12.5v to reset . 4. keep the prog_enable pins unchanged for at least 10s after the high voltage has been applied to ensure the prog_enable signature has been latched. 5. wait until v cc actually reaches 4.5v to 5.5v before giving any parallel programming commands. 6. exit programming mode by powering th e device down or by bringing reset pin to 0v. 24.2.2 considerations for efficient programming loaded commands and addresses are retained in the device duri ng programming. for efficient programming, the following should be considered: when writing or reading multiple memory locati ons, the command only needs to be loaded once. do not write the data value 0xff, beca use this is already the contents of the entire flash and eeprom (unless the eesave fuse is programmed) after a chip erase. address high byte only needs to be loaded before progra mming or reading a new 256-word window in flash or 256- byte eeprom. this also applies to reading signature bytes. 24.2.3 chip erase a chip erase must be performed befor e the flash and/or eeprom ar e reprogrammed. the chip erase command will erase all flash and eeprom plus lock bits. if the eesave fuse is programmed, the eeprom is not erased. lock bits are not reset until the program memory has been completely erased. fuse bits are not changed. the chip erase command is loaded as follows: 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the chip erase command. 4. give clki a positive pu lse. this loads the command. 5. give wr a negative pulse. this star ts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 205 attiny1634 [preliminary datasheet] 9296c?avr?07/14 24.2.4 programming the flash flash is organized in pages as shown in table 24-1 on page 202 . when programming flash, the program data is first latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load the ?write flash? command 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command. 4. give clki a positive pu lse. this loads the command. b. load the address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects the low address. 3. set data = address low byte (0x00 ? 0xff). 4. give clki a positive pulse. this loads the address low byte. c. load the data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 ? 0xff). 3. give clki a positive puls e. this loads the data byte. d. load the data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 ? 0xff). 4. give clki a positive puls e. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes (see figure 24-3 for signal waveforms). f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words wi thin the page, the higher bits address the pages within the flash. this is illustrated in figure 24-2 on page 206 . note that if less than eight bits are required to address words in the page (page size < 256), the most signi ficant bit(s) in the address low byte are used to address the page when per- forming a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects the high address. 3. set data = address high byte (0x00 ? 0xff). 4. give clki a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programm ing of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 24-3 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. ending page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give clki a positive pulse. this loads the command and the internal write signals are reset. attiny1634 [preliminary datasheet] 9296c?avr?07/14 206 flash page addressing is illustrated in figure 24-2 . symbols used are described in table 22-1 on page 192 . figure 24-2. addressing the flash which is organized in pages flash programming waveforms are illustrated in figure 24-3 , where xx means ?don?t care? and letters refer to the programming steps described above. figure 24-3. flash programming waveforms pagemsb pcmsb word address within a page page address within the flash pcword pcpage page instruction word program memory page program counter 02 01 00 pageend pcword [pagemsb : 0] xtal1 rdy/ bsy oe pagel bs2 reset +12v bs1 xa0 xa1 data abcdebcd f e gh 0x10 xx xx xx addr. high addr. low addr. low data high data high data low data low wr 207 attiny1634 [preliminary datasheet] 9296c?avr?07/14 24.2.5 programming the eeprom the eeprom is organi zed in pages (see table 24-2 on page 202 ). when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (for more information on loading the command, address and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0001 0001? g: load address high byte (0x00 ? 0xff) b: load address low byte (0x00 ? 0xff) c: load data (0x00 ? 0xff) e: latch data (give pagel a positive pulse) k: repeat steps b, c, and e unt il the entire buffer is filled. l: programming the eeprom page: set bs1 to ?0?. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. wait until rdy/bsy goes high before programming the next page (see figure 24-4 for signal waveforms) eeprom programming wavefo rms are illustrated in figure 24-4 , where xx means ?don?t care? and letters refer to the programming steps described above. figure 24-4. eeprom pr ogramming waveforms 24.2.6 reading the flash the algorithm for reading the flash memory is as follows (for more information on loading the command and address, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0000 0010? g: load address high byte (0x00 ? 0xff) b: load address low byte (0x00 ? 0xff) set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. set bs1 to ?1?. the flash word high byte can now be read at data. set oe to ?1?. xtal1 rdy/ bsy oe reset +12v bs1 xa0 pagel bs2 xa1 data wr abcebc k e g addr. high addr. low 0x11 data xx addr. low data xx l attiny1634 [preliminary datasheet] 9296c?avr?07/14 208 24.2.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (for more information on loading the command and address, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0000 0011? g: load address high byte (0x00 ? 0xff) b: load address low byte (0x00 ? 0xff) set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. set oe to ?1?. 24.2.8 programming low fuse bits the algorithm for programming the low fuse bits is as follo ws (for more information on loading the command and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0100 0000?. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit give wr a negative pulse and wait for rdy/bsy to go high. 24.2.9 programming high fuse bits the algorithm for programming the high fuse bits is as follow s (for more information on loading the command and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0100 0000?. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit set bs1 to ?1? and bs2 to ?0?. this selects high data byte. give wr a negative pulse and wait for rdy/bsy to go high. set bs1 to ?0?. this selects low data byte. 24.2.10 programming extended fuse bits the algorithm for programming t he extended fuse bits is as follows (for more information on loading the command and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0100 0000?. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. give wr a negative pulse and wait for rdy/bsy to go high. set bs2 to ?0?. this selects low data byte. 209 attiny1634 [preliminary datasheet] 9296c?avr?07/14 fuse programming waveforms are illustrated in figure 24-5 , where xx means ?don?t care? and letters refer to the programming steps described above. figure 24-5. fuses pr ogramming waveforms 24.2.11 programming the lock bits the algorithm for programming the lock bits is as follows (for more information on loading the command and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0010 0000?. c: load data low byte. bit n = ?0? programs the lock bit. if lb1 and lb2 have been programmed, it is not possible to program the lock bits by any external programming mode. give wr a negative pulse and wait for rdy/bsy to go high. lock bits can only be cleared by executing chip erase. 24.2.12 reading fuse and lock bits the algorithm for reading fuse and lock bits is as follows (for more information on loading the command and data, see section 24.2.4 ?programming the flash? on page 205 ): a: load command ?0000 0100?. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. low fuse bi ts can now be read at data (?0? means programmed). set oe to ?0?, bs2 to ?1? and bs1 to ?1?. high fuse bits can now be read at data (?0? means programmed). set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. extended fu se bits can now be read at data (?0? means programmed). set oe to ?0?, bs2 to ?0? and bs1 to ?1?. lock bits can now be read at data (?0? means programmed). set oe to ?1?. xtal1 pagel rdy/ bsy oe reset +12v bs1 bs2 xa0 xa1 data wr ac 0x40 dat a xx ac dat a dat a xx xx ac 0x40 0x40 write fuse low byte write fuse high byte write extended fuse byte attiny1634 [preliminary datasheet] 9296c?avr?07/14 210 fuse and lock bit mapping is illustrated in figure 24-6 . figure 24-6. mapping between bs1, bs2, and the fuse and lock bits during read 24.2.13 reading signature bytes the algorithm for reading the signature bytes is as follows (f or more information on loading the command and address, see section 24.2.4 ?programming the flash? on page 205 ): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 ? 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 24.2.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (for more information on loading the command and address, see section 24.2.4 ?programming the flash? on page 205 ): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. fuse low byte extended fuse byte bs2 bs1 data bs2 lock bits fuse high byte 1 0 1 0 1 0 211 attiny1634 [preliminary datasheet] 9296c?avr?07/14 24.3 serial programming flash and eeprom memory arrays can both be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of the sck, mosi (input), and miso (out put) pins. after reset is set low, the programming enable instruction needs to be executed before program/erase operations can be executed. serial programming signals and connections are illustrated in figure 24-7 below. the pin mapping is listed in table 24-7 on page 211 . figure 24-7. serial programming signals note: if the device is clocked by the internal oscillator, t here is no need to connect a clock source to the clki pin. when programming the eeprom, an auto-erase cycle is built into the self timed programmi ng operation and there is no need to first execute the chip erase instruction. this applies to serial programming mode only. the chip erase operation tu rns the content of every memory location in flash and eeprom arrays into 0xff. depending on cksel fuses, a vali d clock must be present. the minimum low an d high periods for the serial clock (sck) input are defined as follows: minimum low period of serial clock: 2 cpu clock cycles minimum high period of serial clock: 2 cpu clock cycles 24.3.1 pin mapping the pin mapping is listed in table 24-7 . note that not all parts use the spi pins dedicated for the internal spi interface. gnd reset vcc mosi miso sck clki +2.7 to 5.5v table 24-7. pin mapping serial programming symbol pins i/o description mosi pb1 i serial data in miso pb2 o serial data out sck pc1 i serial clock attiny1634 [preliminary datasheet] 9296c?avr?07/14 212 24.3.2 programming algorithm when writing serial data to the atmel ? attiny1634, data is clocked on the rising edge of sck. when reading data from the atmel attiny1634, data is clocked on the falling edge of sck. for more information on timing, see figure 25-7 on page 223 and figure 25-8 on page 223 . to program and verify the atmel attiny1634 in the serial programming mode, the followin g sequence is recommended (see table 24-8 on page 213 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some systems, the program mer cannot guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse after sck has been set to ?0?. the duration of the pulse must be at least t rst plus two cpu clock cycles. see table 25-5 on page 218 for the definition of minimum pulse width on reset pin, t rst . 2. wait for at least 20ms and then enable serial programm ing by sending the programming enable serial instruction to the mosi pin. 3. the serial programming instructions do not work if the co mmunication is out of synchro nization. when in sync, the second byte (0x53) echoes back when issuing the third byte of the programming enable instruction. regardless of whether the echo is co rrect or not, all four bytes of the instruction must be transmitted if the 0x53 does no t echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, data low byte must be loaded before data high byte for a given address is applied. the program memory page is stored by loading the writ e program memory page instruction with the 7msb of the address. if polling (rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page (see table 24-9 ). accessing the serial programming interface bef ore the flash write operation completes can result in incorrect programming. 5. the eeprom can be programmed one byte or one page at a time. a : byte programming. the eeprom array is programmed one byte at a time by supplying the address and data together with the write instruction. eeprom memory locations are autom atically erased before new data is written. if polling (rdy/bsy ) is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 24-9 ). in a chip-erased device, no 0xffs in the data file(s) need to be programmed. b : page programming (the eeprom array is programmed one page at a time). the memory page is loaded one byte at a time by supplying the 6 lsb of the a ddress and data together wit h the load eeprom memory page instruction. the eeprom memory page is stored by loading the wr ite eeprom memory page instruction with the 7msb of the address. when using eeprom, page access only byte locations loaded with the load eeprom memory page instruction are altered and the remaining locations remain unchanged. if polling (rdy/bsy ) is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 24-9 ). in a chip-erased device, no 0xff in the data file(s) needs to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at the serial output pin (miso). 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if required): set reset to ?1?, and turn v cc power off. 213 attiny1634 [preliminary datasheet] 9296c?avr?07/14 24.3.3 programming instruction set the instruction set for serial programming is described in table 24-8 and figure 24-8 on page 214 . notes: 1. not all instructions are applicable for all parts. 2. a = address. 3. instructions accessing program memory use a word a ddress. this address may be random within the page range. 4. word addressing. 5. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?). if the lsb of rdy/bsy data byte out is ?1?, a programming operation is still pending. wait until this bit returns ?0? before the next instruction is carried out. within the same page the low data byte must be loaded prior to the high data byte. after data is loaded to the page bu ffer, program the eeprom page (see figure 24-8 on page 214 ). table 24-8. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa (2) data byte in read instructions read program memory, high byte $28 adrmsb adr lsb high data byte out read program memory, low byte $20 adrmsb adr lsb low data byte out read eeprom memory $a0 0000 00aa (2) aaaa aaaa (2) data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa (2) data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read fuse extended bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (3) write program memory page $4c adrmsb (4) adr lsb (4) $00 write eeprom memory $c0 0000 00aa (2) aaaa aaaa (2) data byte in write eeprom memory page (page access) $c2 0000 00aa (2) aaaa aa00 (2) $00 write lock bits (5) $ac $e0 $00 data byte in write fuse bits (5) $ac $a0 $00 data byte in write fuse high bits (5) $ac $a8 $00 data byte in write fuse extended bits (5) $ac $a4 $00 data byte in attiny1634 [preliminary datasheet] 9296c?avr?07/14 214 figure 24-8. serial programming instruction example 24.4 programming time for flash and eeprom flash and eeprom wait times are listed in table 24-9 . byte 1 byte 2 byte 3 byte 4 page 0 page 1 page 2 adr lbs adr mbs bit 15 b 0 bit 15 b 0 byte 1 byte 2 byte 3 byte 4 adr lbs adr mbs page n-1 program memory eeprom memory serial programming instruction page buffer page number page offset load program memory page (high/low byte)/ load eeprom memory page (page access) write program memory page/ write eeprom memory page table 24-9. typical wait delays before next flash or eeprom location can be written operation minimum wait delay t wd_flash 4.5ms t wd_eeprom 3.6ms t wd_erase 9.0ms 215 attiny1634 [preliminary datasheet] 9296c?avr?07/14 25. electrical characteristics 25.2 dc characteristics 25.1 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters min. max. unit operating temperature ?55 +125 c storage temperature ?65 +150 c voltage on any pin except reset with respect to ground ?0.5 v cc + 0.5 v voltage on reset with respect to ground ?0.5 +13.0 v maximum operating voltage 6.0 v dc current per i/o pin dc current v cc and gnd pins 40 200 ma table 25-1. dc characteristics. t a = ?40c to +125c parameter condition symbol min typ (1) max unit input low voltage v cc = 2.7v to 5.5v v il 0.3v cc (2) v input low-voltage, reset pin as reset (4) v cc = 2.7v to 5.5v 0.2v cc (2) v input high-voltage except reset pin v cc = 2.7v to 5.5v v ih 0.6v cc (3) v cc +0.5 v input high-voltage reset pin as reset (4) v cc = 2.7v to 5.5v 0.9v cc (3) v cc +0.5 v output low-voltage (5) except reset pin (7) standard i/o: i ol = 8ma, v cc = 5v v ol 0.8 v high-sink i/o: i ol = 20ma, v cc = 5v standard i/o: i ol = 5ma, v cc = 3v 0.7 v high-sink i/o: i ol = 10ma, v cc = 3v notes: 1. typical values at +25c. 2. ?max? means the highest value where th e pin is guaranteed to be read as low. 3. ?min? means the lowest value where the pin is guaranteed to be read as high. 4. not tested in production. 5. although each i/o port can sink more than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state conditions (non-transi ent), the sum of all i ol (for all ports) should not exceed 100ma. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaran teed to sink current greater than the listed test condition. 6. although each i/o port can source more than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i oh (for all ports) should not exceed 100ma. if i oh exceeds the test condi- tion, v oh may exceed the related specification. pins are not g uaranteed to source current greater than the listed test condition. 7. the reset pin must tolerate high voltages when entering and operating in programming modes and, as a conse- quence, has a weak drive strength as compared to regular i/o pins (see section 26.7 ?output driver strength? on page 234 ). 8. these are test limits, which account for leakage currents of the test environment. actual device leakage currents are lower. 9. values are with external clock using methods described in section 8.3 ?minimizing power consumption? on page 35 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 10. bod disabled. attiny1634 [preliminary datasheet] 9296c?avr?07/14 216 output high-voltage (6) except reset pin (7) i oh = ?10ma, v cc = 5v v oh 4.3 v i oh = ?5ma, v cc = 3v 2.5 v input leakage current i/o pin vcc = 5.5v, pin low (absolute value) i lil < 0.05 1 (8) a input leakage current i/o pin vcc = 5.5v, pin high (absolute value) i lih < 0.05 1 (8) a pull-up resistor, i/o pin v cc = 5.5v, input low r pu 20 50 k pull-up resistor, reset pin v cc = 5.5v, input low 30 60 k supply current, active mode (9) f = 4mhz, v cc = 3v i cc 1.2 1.8 ma f = 8mhz, v cc = 5v 4.2 8 ma f = 12mhz, v cc = 5v 5.9 10 ma supply current, idle mode (9) f = 4mhz, v cc = 3v 0.23 0.75 ma f = 8mhz, v cc = 5v 1.1 1.5 f = 12mhz, v cc = 5v 1.7 2.2 supply current, power-down mode (10) wdt enabled, v cc = 3v 1.93 30 a wdt disabled, v cc = 3v 0.11 27 a wdt enabled, v cc = 5v 3.85 45 a wdt disabled, v cc = 5v 0.15 40 a table 25-1. dc characteristics. t a = ?40c to +125c (continued) parameter condition symbol min typ (1) max unit notes: 1. typical values at +25c. 2. ?max? means the highest value where th e pin is guaranteed to be read as low. 3. ?min? means the lowest value where the pin is guaranteed to be read as high. 4. not tested in production. 5. although each i/o port can sink more than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state conditions (non-transi ent), the sum of all i ol (for all ports) should not exceed 100ma. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaran teed to sink current greater than the listed test condition. 6. although each i/o port can source more than the test conditions (10ma at v cc = 5v, 5ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i oh (for all ports) should not exceed 100ma. if i oh exceeds the test condi- tion, v oh may exceed the related specification. pins are not g uaranteed to source current greater than the listed test condition. 7. the reset pin must tolerate high voltages when entering and operating in programming modes and, as a conse- quence, has a weak drive strength as compared to regular i/o pins (see section 26.7 ?output driver strength? on page 234 ). 8. these are test limits, which account for leakage currents of the test environment. actual device leakage currents are lower. 9. values are with external clock using methods described in section 8.3 ?minimizing power consumption? on page 35 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 10. bod disabled. 217 attiny1634 [preliminary datasheet] 9296c?avr?07/14 25.3 speed the maximum operating frequency of the de vice depends on the supply voltage (v cc ). the relationship between supply voltage and maximum operating frequency is piece-wise linear as shown in figure 25-1 . figure 25-1. maximum frequency versus v cc 25.4 clock 25.4.1 accuracy of calibr ated 8mhz oscillator it is possible to manually calibrate the in ternal 8mhz oscillator to be more accurate than default factory calibration. note th at the oscillator frequency depends on temperature and voltage . for voltage and temperature characteristics, see section 26-39 ?calibrated oscillator frequency (nominal = 1mhz) versus v cc ? on page 243 and section 26-40 ?calibrated oscillator frequency (nominal = 1mhz) versus temperature? on page 244 . note: 1. .accuracy of oscillator frequency at calibrat ion point (fixed temperature and fixed voltage). 25.4.2 accuracy of calibrated 32khz oscillator it is possible to manually calibrate the inte rnal 32khz oscillator to be more accurate than default factory calibration. note t hat the oscillator frequency depends on temperature and voltage . for voltage and temperature characteristics, see section 26- 41 ?ulp oscillator frequency (nominal = 32khz) versus v cc ? on page 244 and section 26-41 ?ulp oscillator frequency (nominal = 32khz) versus v cc ? on page 244 . 8mhz 12mhz 5.5v 4.5v 2.7v table 25-2. calibration accuracy of internal 8mhz oscillator calibration method target frequency v cc temperature accuracy factory calibration 8.0mhz 3.0v 25c 1.5% (1) 2.7v to 5.5v ?40c to +125c 10% table 25-3. calibration accuracy of internal 32khz oscillator calibration method target frequency v cc temperature accuracy factory calibration 32khz 2.7v to 5.5v ?40c to +125c 33% attiny1634 [preliminary datasheet] 9296c?avr?07/14 218 25.4.3 external clock drive figure 25-2. external clock drive waveform 25.5 system and reset t chcx v ih1 v il1 t chcx t clch t chcl t clcx t clcl table 25-4. external clock drive characteristics parameter symbol v cc = 2.7v to 5.5v v cc = 4.5v to 5.5v unit min. max. min. max. clock frequency 1/t clcl 0 8 0 12 mhz clock period t clcl 125 83 ns high time t chcx 40 20 ns low time t clcx 40 20 ns rise time t clch 1.6 0.5 s fall time t chcl 1.6 0.5 s change in period from one clock cycle to next t clcl 2 2 % table 25-5. reset, brown-out, and internal voltage characteristics parameter condition symbol min typ max unit reset pin threshold voltage v rst 0.2v cc 0.9v cc v minimum pulse width on reset pin v cc = 3v v cc = 5v t rst 2000 (1) 700 400 ns brown-out detector hysteresis v hyst 50 mv minimum pulse width on brown-out reset t bod 2 s internal band-gap reference voltage v cc = 2.7v t a = 25c v bg 1.0 1.1 1.2 v internal band-gap reference start-up time v cc = 2.7v t a = 25c t bg 40 70 s internal band-gap reference current consumption v cc = 2.7v t a = 25c i bg 15 a note: 1. minimum pulse width to guarantee a reset under all usage conditions. 219 attiny1634 [preliminary datasheet] 9296c?avr?07/14 25.5.1 power-on reset note: 1. before rising, the supply has to be between v pormin and v pormax to ensure a reset. 25.5.2 brown-out detection note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 25.6 two-wire serial interface the following data is based on simulations and characterizations. parameters listed in table 25-8 are not tested in production. symbols refer to figure 25-3 . note: 1. f ck = cpu clock frequency. table 25-6. power-on reset specifications parameter symbol min typ max unit power-on reset threshold voltage (rising) v pot 1.1 1.4 1.7 v power-on reset threshold voltage (falling) (1) 0.8 1.3 1.6 v vcc max. start voltage to ensure internal power-on reset signal v pormax 0.4 v vcc min. start voltage to ensure internal power-on reset signal v pormin ?0.1 v vcc rise rate to ensure power-on reset v ccrr 0.01 v/ms reset pin threshold voltage v rst 0.1 v cc 0.9v cc v table 25-7. v bot versus bodlevel fuse coding bodlevel[2:0] fuses min (1) typ (1) max (1) unit 11x 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.0 4.3 4.6 0xx reserved table 25-8. two-wire serial interface characteristics parameter condition symbol min max unit input low voltage v il ?0.5 0.3v cc v input high voltage v ih 0.7v cc v cc + 0.5 v hysteresis of schmitt trigger inputs v cc 2.7v v hys 0.05v cc ? v v cc < 2.7v 0 output low voltage 3ma sink current v ol 0 0.4 v spikes suppressed by input filter t sp 0 50 ns scl clock frequency (1) f ck > max(16f scl , 250khz) f scl 0 400 khz hold time (repeated) start condition t hd:sta 0.6 ? s low period of scl clock t low 1.3 ? s high period of scl clock t high 0.6 ? s setup time for repeated start condition t su:sta 0.6 ? s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ? ns setup time for stop condition t su:sto 0.6 ? s bus free time between stop and start condition t buf 1.3 ? s attiny1634 [preliminary datasheet] 9296c?avr?07/14 220 figure 25-3. two-wire serial bus timing 25.7 analog-to-digital converter sda scl t low t buf t hd:dat t hd:sta t su:dat t su:sto t su:sta t high t r t of t low table 25-9. adc characteristi cs, single-ended channels. t = ?40c to +125c parameter condition symbol min typ max unit resolution 10 bits total unadjusted error v ref = 4v, v cc = 4v, adc clock = 200khz tue 5.0 10 lsb v ref = 4v, v cc = 4v 200khz noise canceler 4.5 8 lsb integral non linearity (inl) (accuracy after offset and gain calibration) v ref = 4v, v cc = 4v, adc clock = 200khz inl 0.6 2.0 lsb v ref = int 1.1v ref, v cc = 4v, adc clock = 200khz. 0.8 2.5 lsb differential non linearity (dnl) v ref = 4v, v cc = 4v, adc clock = 200khz dnl 0.5 0.9 lsb v ref = int 1.1v ref, v cc = 4v, adc clock = 200khz. 0.5 0.95 lsb gain error v ref = 4v, v cc = 4v, adc clock = 200khz ?1.0 0.5 1.0 % offset error v ref = 4v, v cc = 4v, adc clock = 200khz ?40 +20 +40 mv v ref = int 1.1v ref, v cc = 4v, adc clock = 200khz. ?70 +30 +70 mv conversion time free-running conversion 13 25 clocks clock frequency 50 200 khz input voltage v in gnd v ref v input bandwidth 38.5 khz external voltage reference a ref 2.0 v cc v internal voltage reference v int 1.0 1.1 1.2 v reference input resistance at 5v r ref 22.4 32 41.6 k analog input resistance r ain 100 m adc conversion output 0 1023 lsb 221 attiny1634 [preliminary datasheet] 9296c?avr?07/14 25.8 analog comparator 25.9 parallel programming figure 25-4. parallel programming timing, including some general timing requirements figure 25-5. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 25-4 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. table 25-10. analog comparator characteristics, t a = ?40c to +125c parameter condition symbol min typ max unit input offset voltage gnd < v in 223 attiny1634 [preliminary datasheet] 9296c?avr?07/14 25.10 serial programming figure 25-7. serial programming timing figure 25-8. serial programming waveform mosi sck miso t ovsh t shox t shsl t slsh msb serial data input (mosi) serial data output (miso) msb lsb lsb serial clock input (sck) sample table 25-12. serial programm ing characteristics, t a = ?40c to +125c parameter symbol min typ max unit oscillator frequency at v cc = 2.7v to 5.5v 1/t clcl 0 1 mhz oscillator period at v cc = 2.7v to 5.5v t clcl 1000 ns oscillator frequency at v cc = 4.5v to 5.5v 1/t clcl 0 6 mhz oscillator period at v cc = 4.5v to 5.5v t clcl 167 ns sck pulse width high t shsl 2 t clcl ns sck pulse width low t slsh 2 t clcl ns mosi setup to sck high t ovsh t clcl ns mosi hold after sck high t shox 2 t clcl ns attiny1634 [preliminary datasheet] 9296c?avr?07/14 224 26. typical characteristics the data contained in this section is largely based on simu lations and characterization of similar devices in the same process and design methods. thus, the data should be treated as indications of how the part will behave. the following charts show typical behavior. these figures are not tested during manufacturing. during characterisation, devices are operated at frequencies higher than test limits but they are not guarante ed to function properly at frequencies higher than the ordering code indicates. all current consumption measurements ar e performed with all i/o pins configured as inputs and with internal pull-ups enabled. current consumption is a function of several factors su ch as operating voltage, operat ing frequency, loading of i/o pins, switching rate of i/o pins, code ex ecuted, and ambient temperature. the domi nating factors are operating voltage and frequency. a sine wave generator with rail-to-rail output is used as the clock source, but current consumption in power-down mode does not depend on clock selection. the difference between cu rrent consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled re presents the differential current drawn by the watchdog timer. the current drawn from pins with a capacitive lo ad may be estimated (for one pin) as follows: where v cc = operating voltage, c l = load capacitance, and f sw = average switching frequency of i/o pin. 26.1 current consumption in active mode figure 26-1. active supply current versus low fre quency (0.1mhz to 1.0mhz), ?40c up to +125c cp v cc c l f sw 225 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-2. active supply current versus frequency (1mhz to 12mhz), ?40c up to +125c figure 26-3. active supply current versus v cc (internal oscillator, 8mhz) attiny1634 [preliminary datasheet] 9296c?avr?07/14 226 figure 26-4. active supply current versus v cc (internal oscillator, 1mhz) figure 26-5. active supply current versus v cc (internal oscillator, 32khz) 227 attiny1634 [preliminary datasheet] 9296c?avr?07/14 26.2 current consumption in idle mode figure 26-6. idle supply current versus low frequency (0.1mhz - 1.0mhz), ?40c up to +125c figure 26-7. idle supply current versus frequency (1mhz - 12mhz), ?40c up to +125c attiny1634 [preliminary datasheet] 9296c?avr?07/14 228 figure 26-8. idle supply current versus v cc (internal oscillator, 8mhz) figure 26-9. idle supply current versus v cc (internal oscillator, 1mhz) 229 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-10. idle supply current versus v cc (internal oscillator, 32khz) 26.3 current consumption in power-down mode figure 26-11. power-down supply current versus v cc (watchdog timer disabled) attiny1634 [preliminary datasheet] 9296c?avr?07/14 230 figure 26-12. power-down supply current versus v cc (watchdog timer enabled) 26.4 current consumption of peripheral units figure 26-13. reset current versus v cc , excluding current through the reset pull-up and no clock 231 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-14. brown-out detector current versus v cc , normal bod figure 26-15. sampled brown-out detector current versus v cc , sampled bod, average of five current measurements attiny1634 [preliminary datasheet] 9296c?avr?07/14 232 26.5 pull-up resistors figure 26-16. i/o pin pull-up resist or current versus input voltage (v cc = 5v) 26.6 input thresholds figure 26-17. v ih : input threshold voltage versus v cc (i/o pin, read as ?1?) 233 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-18. v il : input threshold voltage versus v cc (i/o pin, read as ?0?) figure 26-19. v ih -v il : input hysteresis versus v cc (reset pin as i/o) attiny1634 [preliminary datasheet] 9296c?avr?07/14 234 26.7 output driver strength figure 26-20. v oh : i/o pin output voltage versus so urce current, low-power pins (v cc = 3v) figure 26-21. v oh : i/o pin output voltage versus so urce current, low-power pins (v cc = 5v) 235 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-22. v ol : i/o pin output voltage versus sink current, low-power pins (v cc = 3v) figure 26-23. v ol : i/o pin output voltage versus sink current, low-power pins (v cc = 5v) attiny1634 [preliminary datasheet] 9296c?avr?07/14 236 figure 26-24. v oh : reset pin output voltage versus sink current (reset pin as i/o, v cc = 3v) figure 26-25. v oh : reset pin output voltage versus sink current (reset pin as i/o, v cc = 5v) 237 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-26. v ol : reset pin output voltage versus sink current (reset pin as i/o, v cc = 5v) figure 26-27. v ol : reset pin output voltage versus sink current (reset pin as i/o, v cc = 3v) attiny1634 [preliminary datasheet] 9296c?avr?07/14 238 26.8 bod figure 26-28. bod threshold versu s temperature, (bodlevel = 4.3v) figure 26-29. bod threshold versu s temperature (bodlevel = 2.7v) 239 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-30. sampled bod threshold versus temperature (bodlevel = 4.3v) figure 26-31. sampled bod threshold versus temperature (bodlevel = 2.7v) attiny1634 [preliminary datasheet] 9296c?avr?07/14 240 26.9 band-gap voltage figure 26-32. band-gap voltage versus temperature 26.10 reset figure 26-33.v ih : input threshold voltage versus v cc (reset pin, read as ?1?) 241 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-34.v il : input threshold voltage versus v cc (reset pin, read as ?0?) figure 26-35. minimum reset pulse width versus v cc attiny1634 [preliminary datasheet] 9296c?avr?07/14 242 26.11 internal oscillator speed figure 26-36. calibrated oscillator frequency (nominal = 8mhz) versus v cc figure 26-37. calibrated os cillator frequency (nominal = 8mhz) versus temperature 243 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 26-38. calibrated os cillator frequency (nominal = 8mhz) versus osccal value figure 26-39. calibrated oscillator frequency (nominal = 1mhz) versus v cc attiny1634 [preliminary datasheet] 9296c?avr?07/14 244 figure 26-40. calibrated os cillator frequency (nominal = 1mhz) versus temperature figure 26-41. ulp oscillator freq uency (nominal = 32khz) versus v cc 245 attiny1634 [preliminary datasheet] 9296c?avr?07/14 27. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? ... ... ... ... ... ... ... ... ... ... ... (0x85) reserved ? ? ? ? ? ? ? ? (0x84) reserved ? ? ? ? ? ? ? ? (0x83) reserved ? ? ? ? ? ? ? ? (0x82) reserved ? ? ? ? ? ? ? ? (0x81) reserved ? ? ? ? ? ? ? ? (0x80) reserved ? ? ? ? ? ? ? ? (0x7f) twscra twshe ? twdie twasie twen twsie twpme twsme 121 (0x7e) twscrb twaa twcmd[1:0] 122 (0x7d) twssra twdif twasif twch twra twc twbe twdir twas 123 (0x7c) twsa twi slave address register 124 (0x7b) twsam twi slave address mask register 125 (0x7a) twsd twi slave data register 124 (0x79) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 157 (0x78) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 158 (0x77) ucsr1c umsel11 umsel10 upm11 upm01 usbs1 ucsz11 ucsz10 ucpol1 159 (0x76) ucsr1d rxsie1 rxs1 sfde1 160 (0x75) ubrr1h usart1 baud rate register high byte 161 (0x74) ubrr1l usart1 baud rate register low byte 161 (0x73) udr1 usart1 i/o data register 156 (0x72) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 106 (0x71) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 108 (0x70) tccr1c foc1a foc1b ? ? ? ? ? ? 109 (0x6f) tcnt1h timer/counter1 ? counter register high byte 109 (0x6e) tcnt1l timer/counter1 ? counter register low byte 109 (0x6d) ocr1ah timer/counter1 ? compare register a high byte 109 (0x6c) ocr1al timer/counter1 ? compare register a low byte 109 (0x6b) ocr1bh timer/counter1 ? compare register b high byte 110 (0x6a) ocr1bl timer/counter1 ? compare register b low byte 110 (0x69) icr1h timer/counter1 ? input capture register high byte 110 (0x68) icr1l timer/counter1 ? input capture register low byte 110 notes: 1. for compatibility with future devi ces, reserved bits should be written to ?0? if acce ssed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logic one to them. note that, unlike most other avr ? s, the cbi and sbi instructions only operate the specified bit and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. attiny1634 [preliminary datasheet] 9296c?avr?07/14 246 (0x67) gtccr tsm ? ? ? ? ? ?psr10 113 (0x66) osccal1 ? ? ? ? ? ? cal11 cal10 33 (0x65) osctcal0b oscillator temperature compensation register b 33 (0x64) osctcal0a oscillator temperature compensation register a 32 (0x63) osccal0 cal07 cal06 cal05 cal04 cal03 cal02 cal01 cal00 32 (0x62) didr2 ? ? ? ? ? adc11d adc10d adc9d 187 (0x61) didr1 ? ? ? ? adc8d adc7d adc6d adc5d 186 (0x60) didr0 adc4d adc3d adc2d adc1d adc0d ain1d ain0d arefd 171 , 186 0x3f (0x5f) sreg i t h s v n z c 15 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 14 0x3c (0x5c) gimsk ? int0 pcie2 pcie1 pcie0 ? ? ? 50 0x3b (0x5b) gifr ? intf0 pcif2 pcif1 pcif0 ? ? ? 51 0x3a (0x5a) timsk toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a 86 , 110 0x39 (0x59) tifr tov1 ocf1a ocf1b ?icf1ocf0btov0ocf0a 86 , 111 0x38 (0x58) qtcsr qtouch control and status register 7 0x37 (0x57) spmcsr ? ? rsig ctpb rflb pgwrt pgers spmen 194 0x36 (0x56) mcucr ?sm1sm0se ? ?isc01isc00 37 , 50 0x35 (0x55) mcusr ? ? ? ? wdrf borf extrf porf 45 0x34 (0x54) prr ? prtwi prtim0 prtim0 prusi prusart1 prusart0 pradc 37 0x33 (0x53) clkpr ? ? ? ? clkps3 clkps2 clkps1 clkps0 31 0x32 (0x52) clksr oscrdy cstr ckout_io sut cksel3 cksel2 cksel1 cksel0 29 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) wdtcsr wdif wdie wdp3 ? wde wdp2 wdp1 wdp0 45 0x2f (0x4f) ccp cpu change protection register 14 0x2e (0x4e) dwdr dwdr[7:0] 189 0x2d (0x4d) usibr usi buffer register 136 0x2c (0x4c) usidr usi data register 136 0x2b (0x4b) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 135 0x2a (0x4a) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 133 0x29 (0x49) pcmsk2 ? ? pcint17 pcint16 pcint15 pcint14 pcint13 pcint12 51 0x28 (0x48) pcmsk1 ? ? ? ? pcint11 pcint10 pcint9 pcint8 52 0x27 (0x47) pcmsk0 pcint7 pcint6 pcin t5 pcint4 pcint3 pcint2 pcint1 pcint0 52 0x26 (0x46) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm 157 0x25 (0x45) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 158 0x24 (0x44) ucsr0c umsel01 umsel00 upm0 1 upm00 usbs0 ucsz01 ucsz00 ucpol0 159 0x23 (0x43) ucsr0d rxcie0 rxs0 sfde0 ? ? ? ? ? 160 0x22 (0x42) ubrr0h ? ? ? ? usart0 baud rate register high byte 161 27. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) notes: 1. for compatibility with future devi ces, reserved bits should be written to ?0? if acce ssed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logic one to them. note that, unlike most other avr ? s, the cbi and sbi instructions only operate the specified bit and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 247 attiny1634 [preliminary datasheet] 9296c?avr?07/14 0x21 (0x41) ubrr0l usart0 baud rate register low byte 161 0x20 (0x40) udr0 usart0 i/o data register 156 0x1f (0x3f) eearh ? ? ? ? ? ? ? ? 0x1e (0x3e) eearl eear[7:0] 22 0x1d (0x3d) eedr eeprom data register 23 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 23 0x1b (0x3b) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 82 0x1a (0x3a) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 84 0x19 (0x39) tcnt0 timer/counter0 85 0x18 (0x38) ocr0a timer/counter0 ? compare register a 85 0x17 (0x37) ocr0b timer/counter0 ? compare register b 85 0x16 (0x36) gpior2 general purpose register 2 24 0x15 (0x35) gpior1 general purpose register 1 24 0x14 (0x34) gpior0 general purpose register 0 24 0x13 (0x33) portcr ? ? ? ? ? bbmc bbmb bbma 69 0x12 (0x32) puea puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 69 0x11 (0x31) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 69 0x10 (0x30) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 69 0x0f (0x2f) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 70 0x0e (0x2e) pueb ? ? ? ? pueb3 pueb2 pueb1 pueb0 70 0x0d (0x2d) portb ? ? ? ? portb3 portb2 portb1 portb0 70 0x0c (0x2c) ddrb ? ? ? ? ddb3 ddb2 ddb1 ddb0 70 0x0b (0x2b) pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 70 0x0a (0x2a) puec ? ? puec5 puec4 puec3 puec2 puec1 puec0 70 0x09 (0x29) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 70 0x08 (0x28) ddrc ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 71 0x07 (0x27) pinc ? ? pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 71 0x06 (0x26) acsra acd acbg aco aci acie acic acis1 acis0 170 0x05 (0x25) acsrb hsel hlev aclp ? acce acme acirs1 acirs0 171 0x04 (0x24) admux refs1 refs0 refen adc0en mux3 mux2 mux1 mux0 182 0x03 (0x23) adcsra aden adsc adate adif adie adps2 adps1 adps0 184 0x02 (0x22) adcsrb vden vdpd ? ? adlar adts2 adts1 adts0 185 0x01 (0x21) adch adc data register high byte 185 0x00 (0x20) adcl adc data register low byte 185 27. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) notes: 1. for compatibility with future devi ces, reserved bits should be written to ?0? if acce ssed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logic one to them. note that, unlike most other avr ? s, the cbi and sbi instructions only operate the specified bit and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. attiny1634 [preliminary datasheet] 9296c?avr?07/14 248 28. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from register rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions jmp k direct jump pc k none 3 rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 call k direct subroutine pc k none 4 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 249 attiny1634 [preliminary datasheet] 9296c?avr?07/14 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3.. 0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set two?s complement overflow. v 1 v 1 clv clear two?s complement overflow v 0 v 1 set set t in sreg t 1 t 1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 28. instruction set summary (continued) mnemonics operands description operation flags #clocks attiny1634 [preliminary datasheet] 9296c?avr?07/14 250 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, r r store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd p none 1 out p, r r out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific des cription for sleep function) none 1 wdr watchdog reset (see specific description for wdr/timer) none 1 break break for on-chip debug only none n/a 28. instruction set summary (continued) mnemonics operands description operation flags #clocks 251 attiny1634 [preliminary datasheet] 9296c?avr?07/14 29. ordering information notes: 1. for speed versus supply voltage, see section 25.3 ?speed? on page 217 . 2. all packages are pb-free, halide-free and fully green, and they comply with the european directive for restric- tion of hazardous substances (rohs). 30. packaging information table 29-1. ordering information atmel attiny1634 speed (mhz) (1) supply voltage (v) temperature range package (2) ordering code 12 2.7 to 5.5 automotive (?40c to +125c) 6g tiny1634-15xz pc tiny1634-15mz table 30-1. atmel attiny1634 package types package types 6g 6g - 20 lead - 4.4mmx6.5mm body - 0.65mm pitch - lead length:0.6mm - thin shrink small outline pc pc - 20 lead - 4.0mmx4.0mm body - 0.50mm pitch - quad flat no-lead package attiny1634 [preliminary datasheet] 9296c?avr?07/14 252 figure 30-1. 6g package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6g a 20/12/07 6g, 20 leads - 4.4x6.5mm body - 0.65mm pitch - lead length: 0.6mm thin shrink small outline index area n 0.10 ( . 004 ) 0.25 ( . 010 ) h c c l a a mm a 1.10 .043 a1 0.15 0.05 .002 .006 b0.30 0.19 .007 .012 c0.20 0.09 .003 .008 d6.60 6.40 .252 .260 e4.50 4.30 .169 .177 l n20 q 0 ~8 0 ~8 20 0.70 0.50 .020 .028 e bsc 0.65 .026 bsc inch seating plane q a1 0 md d d e d c a - b e b h bsc 6.40 .252 bsc 253 attiny1634 [preliminary datasheet] 9296c?avr?07/14 figure 30-2. pc package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title pc i 06/25/09 pc, 20-lead - 4.0x4.0mm body, 0.50mm pitch quad flat no lead package (qfn) top view bottom view side view d e 1.00 ref see option a, b, c 1 nnn 11 option a pin 1# chamfer (c 0.30) pin 1# notch (0.20 r) pin 1# triangle option b option c 0.15 (4x) 0.08 c 0.10 c c j a b e2 d2 e l 1 n seating plane drawings not scaled compliant jedec standard mo-220 variation wggd-5 common dimensions in mm symbol min. nom. max. a 0.70 0.75 0.80 d/e 3.90 4.00 4.10 l 0.35 0.45 0.55 b 0,20 0.25 0.30 d2/e2 2.50 2.60 n20 e 0.50 bsc 2.70 j 0.00 0.05 notes pin #1 identifier laser marking 1.00 ref attiny1634 [preliminary datasheet] 9296c?avr?07/14 254 31. errata the revision letters in this section refer to the revisi on of the corresponding atmel ? attiny1634 device. 31.1 atmel attiny1634 31.1.1 rev. b port pin should not be used as input when ulp oscillator is disabled. 1. port pin should not be used as input when ulp oscillator is disabled. port pin pb3 is not guaranteed to perform as a reliable input when the ultra-low-power (ulp) oscillator is not running. in addition, the pin is pulled down internal ly when the ulp oscillator is disabled. problem fix/workaround the ulp oscillator is automatically activated when required. to use pb3 as an input, activate the watchdog timer. the watchdog timer automatically enables the ulp oscillator. 32. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9296c-avr-07/14 ? section 20-1 ?features on page 172 updated ? section 25.2 ?dc characteristics? on pages 215 to 216 updated ? table 25-2 ?calibration accuracy of internal 8mhz oscillator? on page 217 updated ? table 25-3 ?calibration accuracy of internal 32khz oscillator? on page 217 updated ? table 25-5 ?reset, brown-out, and internal vo ltage characteristics? on page 218 updated ? section 25.7 ?analog-to-digital converter? on page 220 updated ? section 25.8 ?analog comparator? on page 221 updated ? put datasheet in the latest template 9296b-avr-12/13 ? section 25.2 ?dc characteristics? on page 215 updated 255 attiny1634 [preliminary datasheet] 9296c?avr?07/14 33. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. automotive quality grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 alu ? arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 general purpose register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.5 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 instruction execution timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7 reset and interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 program memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 data memory (sram) and register files . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 data memory (eeprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 clock subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 system clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 clock output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 power reduction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3 minimizing power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9. system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 resetting the avr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 attiny1634 [preliminary datasheet] 9296c?avr?07/14 256 11. i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2 ports as a general digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12. 8-bit timer/counter0 with pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.4 counter unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.5 output compare unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.6 compare match output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.7 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.8 timer/counter timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13. 16-bit timer/counter1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.3 timer/counter clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.4 counter unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.5 input capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 output compare units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 compare match output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 timer/counter timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.10 accessing 16-bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14. timer/counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.1 prescaler reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 15. i2c-compatible, two-wire slave interface . . . . . . . . . . . . . . . . . . . . . . 114 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15.3 general twi bus concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15.4 twi slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16. usi ? universal serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 16.3 three-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.4 two-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.5 alternative use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.6 program examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16.7 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 17. usart (usart0 and usart1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 17.2 usart0 and usart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 17.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 17.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 17.5 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 257 attiny1634 [preliminary datasheet] 9296c?avr?07/14 17.6 usart initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 17.7 data transmission ? the usart transmitter . . . . . . . . . . . . . . . . . . . . 143 17.8 data reception ? the usart receiver . . . . . . . . . . . . . . . . . . . . . . . . . 146 17.9 asynchronous data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 17.10 multiprocessor communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . 153 17.11 examples of baud rate setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 17.12 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 18. usart in spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.3 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.4 spi data modes and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.5 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.6 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 18.7 compatibility with avr spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 18.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 19. analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 19.1 analog comparator multiplexed input . . . . . . . . . . . . . . . . . . . . . . . . . . 169 19.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 20. analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 20.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 20.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 20.4 starting a conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 20.5 prescaling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 20.6 changing channel or reference selection . . . . . . . . . . . . . . . . . . . . . . 178 20.7 adc noise canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 20.8 analog input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 20.9 noise canceling techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 20.10 adc accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 20.11 adc conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 20.12 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 20.13 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 21. debugwire on-chip debug system . . . . . . . . . . . . . . . . . . . . . . . . . . 188 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 21.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 21.3 physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 21.4 software break points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 21.5 limitations of debugwire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 21.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 22. self programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 22.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 22.3 lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 22.4 self programming the flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 22.5 preventing flash corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 22.6 programming time for flash when using spm . . . . . . . . . . . . . . . . . . . 194 22.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 attiny1634 [preliminary datasheet] 9296c?avr?07/14 258 23. lock bits, fuse bits and device signature . . . . . . . . . . . . . . . . . . . . . . 196 23.1 lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 23.2 fuse bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 23.3 device signature imprint table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 23.4 reading lock, fuse, and signature data from software . . . . . . . . . . . . 200 24. external programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 24.1 memory parametrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 24.2 parallel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 24.3 serial programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 24.4 programming time for flash and eeprom . . . . . . . . . . . . . . . . . . . . . . 214 25. electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 25.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 25.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 25.3 speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 25.4 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 25.5 system and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 25.6 two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 25.7 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 25.8 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 25.9 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 25.10 parallel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 25.11 serial programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 26. typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 26.1 current consumption in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 26.2 current consumption in idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 26.3 current consumption in power-down mode . . . . . . . . . . . . . . . . . . . . . 229 26.4 current consumption of peripheral units . . . . . . . . . . . . . . . . . . . . . . . . 230 26.5 pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 26.6 input thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 26.7 output driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 26.8 bod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 26.9 band-gap voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 26.10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 26.11 internal oscillator speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 27. register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 28. instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 29. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 30. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 31. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 31.1 atmel attiny1634 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 32. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 33. table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: rev.: 9296c?avr?07/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade. |
Price & Availability of ATTINY1634-14
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |